PHASE LOCKED LOOP CIRCUIT AND RECEIVER USING THE SAME

• US 20100195779A1
• Filed: 09/03/2009
• Published: 08/05/2010
• Est. Priority Date: 02/04/2009
• Status: Active Grant

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Sai, Akihide
• Granted Patent: US 8,615,064 B2
• Time in Patent Office: Days
• US Class Current: 375/376
• CPC Class Codes: H03L 7/087 using at least two phase detectors or a frequency and phase detector in the loop
• CPC Class Codes: H03L 7/0996 Selecting a signal among the plurality of phase-shifted signals produced by the ring oscillator
• CPC Class Codes: H03L 7/113 using frequency discriminator

Abstract

A phase locked loop circuit which obtains an output signal coincident in frequency and phase with a target signal which is acquired by multiplying the frequency of a reference signal by a ratio represented by the sum of a first fraction and a second fraction, the circuit includes a controlled oscillator including the same number of stages of annularly connected amplifiers as a number which is obtained by dividing, by 2, a least common multiple of a denominator of the first fraction, a denominator of the second fraction and 2, the same number of multiphase signals as the least common multiple being extractable from the controlled oscillator, the frequency of the multiphase signals being controlled by a digital control signal and an analog control signal, one of the multiphase signals being output as the output signal.

Claims

1. A phase locked loop circuit which obtains an output signal coincident in frequency and phase with a target signal which is acquired by multiplying the frequency of a reference signal by a ratio represented by the sum of a first fraction and a second fraction, the circuit comprising:

a controlled oscillator including the same number of stages of annularly connected amplifiers as a number which is obtained by dividing, by 2, a least common multiple of a denominator of the first fraction, a denominator of the second fraction and 2, the same number of multiphase signals as the least common multiple being extractable from the controlled oscillator, the frequency of the multiphase signals being controlled by a digital control signal and an analog control signal, one of the multiphase signals being output as the output signal;

a converter which converts a frequency difference and a phase difference between the output signal and the reference signal to a first digital signal;

a digital phase frequency detector which subtracts the first digital signal from a second digital signal representing the ratio and obtains a third digital signal representing a frequency difference and a phase difference between the output signal and the target signal;

a digital filter which performs filter processing of smoothing the third digital signal to generate the digital control signal;

a signal selector which sequentially selects, from the multiphase signals at every period of the reference signal in accordance with the first digital signal, a signal in phase with the reference signal in a next period as a selected signal;

an analog phase detector which obtains an analog phase difference signal representing a phase difference between the selected signal and the reference signal;

an analog filter which performs filter processing of smoothing the analog phase difference signal to generate the analog control signal; and

a lock detector which switches signal paths for the analog control signal so that the analog control signal is provided to the controlled oscillator when the lock detector detects in accordance with the third digital signal that the output signal and the target signal are coincident in frequency and phase.

2. The circuit according to claim 1, wherein the digital phase frequency detector, the digital filter, the controlled oscillator and the converter form a first loop having a first loop band, and

the analog phase detector, the analog filter, the controlled oscillator and the selector form a second loop having a second loop band broader than the first loop band.

3. The circuit according to claim 1, wherein the amplifiers are single-phase amplifiers.

4. The circuit according to claim 1, wherein the amplifiers are differential amplifiers.

5. The circuit according to claim 1, further comprising an amplifier which amplifies the level of the analog control signal and provides a resultant analog control signal to the controlled oscillator.

12. A receiver comprising:

a clock generator which includes the circuit according to claim 1 and which generates the output signal as a clock signal; and

an analog-digital converter which performs sampling in accordance with the clock signal.

6. A phase locked loop circuit which obtains an output signal coincident in frequency and phase with a target signal which is acquired by multiplying the frequency of a reference signal by a ratio represented by the sum of a first fraction and a second fraction, the circuit comprising:

a controlled oscillator including the same number of stages of annularly connected amplifiers as a number which is obtained by dividing, by 2, a least common multiple of a denominator of the first fraction, a denominator of the second fraction and 2, the same number of multiphase signals as the least common multiple being extractable from the controlled oscillator, the frequency of the multiphase signals being controlled by a digital control signal and an analog control signal, one of the multiphase signals being output as the output signal;

a converter which converts a frequency difference and a phase difference between the output signal and the reference signal to a first digital signal;

a digital phase frequency detector which subtracts the first digital signal from a second digital signal representing the ratio and obtains a third digital signal representing a frequency difference and a phase difference between the output signal and the target signal;

a digital filter which performs filter processing of smoothing the third digital signal to generate the digital control signal;

a signal selector which sequentially selects, from the multiphase signals at every period of the reference signal in accordance with the first digital signal, a signal in phase with the reference signal in a next period as a first selected signal, a signal whose phase is ahead the phase of the first selected signal as a second selected signal, and a signal whose phase is behind the phase of the first selected signal as a third selected signal;

an analog phase detector which obtains a first analog signal representing a phase difference between one of the second and third selected signals and the reference signal, and a second analog signal representing a phase difference between the other of the second and third selected signals and the first selected signal;

an analog filter which performs filter processing of smoothing the first analog signal and the second analog signal to generate the analog control signal; and

a lock detector which switches signal paths for the analog control signal so that the analog control signal is provided to the controlled oscillator when the lock detector detects in accordance with the third digital signal that the output signal and the target signal are coincident in frequency and phase.

7. The circuit according to claim 6, wherein the digital phase frequency detector, the digital filter, the controlled oscillator and the converter form a first loop having a first loop band, and

the analog phase detector, the analog filter, the controlled oscillator and the selector form a second loop having a second loop band broader than the first loop band.

8. The circuit according to claim 6, wherein the analog control signal is a differential signal.

9. The circuit according to claim 6, wherein the amplifiers are single-phase amplifiers.

10. The circuit according to claim 6, wherein the amplifiers are differential amplifiers.

11. The circuit according to claim 6, further comprising an amplifier which amplifies the level of the analog control signal and provides a resultant analog control signal to the controlled oscillator.