PROCESS AND TEMPERATURE INSENSITIVE FLICKER NOISE MONITOR CIRCUIT

• US 20100197053A1
• Filed: 04/16/2010
• Published: 08/05/2010
• Est. Priority Date: 04/02/2008
• Status: Active Grant

• Current Assignee: Baher S. Haroun, Gaurav Chandra, Hisashi Shichijo, Krishnaswamy Nagaraj, Venkatesh Srinivasan, Vijaya Bhaskar Rentala
• Original Assignee: Baher S. Haroun, Gaurav Chandra, Hisashi Shichijo, Krishnaswamy Nagaraj, Venkatesh Srinivasan, Vijaya Bhaskar Rentala
• Inventors: Shichijo, Hisashi, Nagaraj, Krishnaswamy, Chandra, Gaurav, Rentala, Vijaya Bhaskar, Haroun, Baher S., Srinivasan, Venkatesh
• Granted Patent: US 7,915,905 B2
• Time in Patent Office: Days
• US Class Current: 438/18
• CPC Class Codes: H01L 22/34 Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line switching, multiplexing, gating devices G01R19/25; process control with lithography, e.g. dose control, G03F7/20; structures for alignment control by optical means G03F7/70633
• CPC Class Codes: H03M 3/35 using redundancy
• CPC Class Codes: H03M 3/43 the quantiser being a single bit one
• CPC Class Codes: H03M 3/438 the modulator having a higher order loop filter in the feedforward path

Abstract

In an apparatus and method for monitoring defects in wafers, a monitoring circuit is fabricated on an area of each one of the wafers. The monitoring circuit includes representative devices that replicate similar devices located in a die area of the wafers. Defects if present in the representative devices contribute to a generation of a noise, thereby causing an imbalance in a differential signal measurable across selected ones of the representative devices. A digitizing circuit that uses a common mode voltage as a reference to measure the imbalance digitizes the differential signal to a digital signal, the digital signal being indicative of the noise generated by the defects. The digital signal is stored over a configurable time interval to form a digital bit stream. The digital bit stream is compared to a reference to determine whether the defeats are within an allowable range.

Claims

1. A method for monitoring defects in wafers, the method comprising:

selecting at least one area on each one of the wafers to fabricate a monitoring circuit, wherein the monitoring circuit includes representative devices to replicate similar devices located in a die area of the wafers;

measuring a differential signal generated by selected ones of the representative devices located on each one of the wafers, the differential signal being indicative of a noise caused by the defects present in the selected ones; and

digitizing the differential signal to provide a digital signal, the digitizing being performed by the monitoring circuit.

2. The method of claim 1 further comprising:

generating a digital code sequence from the digital signal, the digital code sequence corresponding to the noise measured for each one of the wafers over a configurable time interval; and

storing the digital code sequence.

3. The method of claim 2, wherein the digital code sequence is stored in a corresponding one of the wafers.

4. The method of claim 2 further comprising:

comparing the digital code sequence to a reference code sequence to determine if the noise is within an allowable range.

5. The method of claim 1, wherein the monitoring circuit includes the representative devices electrically coupled to a digitizer circuit, wherein the digitizer circuit is operable to digitize the differential signal.

6. The method of claim 5, wherein the measuring includes:

configuring the selected ones to operate as a diode; and

calibrating the digitizer circuit, wherein the calibrating provides initial power to the representative devices, thereby enabling the selected ones to generate a common mode voltage used as a reference for subsequent measurements.

7. The method of claim 6, wherein the noise is measured as a ratio of the common mode voltage.

8. The method of claim 6, wherein the measuring of the noise as the ratio of the common mode voltage is substantially independent of a process, voltage, and temperature variation experienced by the digitizer circuit.

9. The method of claim 1, wherein the differential signal is 0 volts, the 0 volts being indicative of an absence of the noise.

10. The method of claim 1, wherein the at least one area is a scribe area, the scribe area being electrically isolated from the die area.

11. The method of claim 10, wherein the scribe area is within a configurable distance from the die area.

12. The method of claim 1, wherein the noise is a flicker noise, the flicker noise being generated by the defects present in a material or a process used to fabricate the wafers.

13-28. -28. (canceled)