Digital Signal Processor Having Instruction Set With An Xk Function Using Reduced Look-Up Table

• US 20100198893A1
• Filed: 01/30/2009
• Published: 08/05/2010
• Est. Priority Date: 01/30/2009
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Chen, Jian-Guo, Azadet, Kameran, Hijazi, Samer, Williams, Joseph
• Granted Patent: US 9,207,910 B2
• Time in Patent Office: Days
• US Class Current: 708/209
• CPC Class Codes: G06F 1/035 Reduction of table size G06F1/0314 takes precedence
• CPC Class Codes: G06F 2101/10 Logarithmic or exponential functions
• CPC Class Codes: G06F 7/556 Logarithmic or exponential functions

Abstract

A digital signal processor is provided having an instruction set with an x^K function that uses a reduced look-up table. The disclosed digital signal processor evaluates an x^K function for an input value, x, by computing Log(x) in hardware; multiplying the Log(x) value by K; and determining the x^K function by applying an exponential function in hardware to a result of the multiplying step. One or more of the computation of Log(x) and the exponential function employ at least one look-up table having entries with a fewer number of bits than a number of bits in the input value, x.

Claims

1. A method performed by a digital signal processor for evaluating an x^K function for an input value, x, said method comprising:

computing Log(x) in hardware;

multiplying said Log(x) value by K; and

determining said x^K function by applying an exponential function in hardware to a result of said multiplying step, wherein one or more of said computation of Log(x) and said exponential function employ at least one look-up table having entries with a fewer number of bits than a number of bits in the input value, x.

2. The method of claim 1, where said Log(x) value is obtained by decomposing the input value, x, to a first part, N, a second part, q, and a remaining part, r, wherein the first part, N, is identified by a position of a most significant bit of the input value, x, and the second part, q, is comprised of a number of bits following said most significant bit, wherein said number is small relative to a number of bits in the input value, x.

3. The method of claim 2, further comprising the step of obtaining a value

4. The method of claim 2, further comprising the step of computing an epsilon term, ε

, using the expression

5. The method of claim 4, wherein said epsilon term, ε

, is computed by shifting r by N and multiplying by

6. The method of claim 4, further comprising the step of evaluating an expression Log₂(1+ε

) using a polynomial approximation.

7. The method of claim 2, wherein said logarithm function is determined for the input value, x, by summing values of N,

8. The method of claim 7, further comprising the step of translating an initial basis for said log(x) function to an arbitrary basis, Y, by multiplying a result of said summing step by Log_Y(2), where log_Y(2), is obtained from a look-up table.

9. The method of claim 1, where said exponential function of said result is obtained by decomposing the input value, x, to an integer part, N, a first fractional part, q₁, larger than a specified value, x₀, and a second fractional part, q₂, smaller than the specified value, x₀.

10. The method of claim 9, wherein a value 2^q2 is computed using a polynomial approximation.

11. The method of claim 9, wherein a value 2^q1 is obtained from a look-up table.

12. The method of claim 9, wherein said exponential function for said result is obtained by multiplying 2^q2, 2^q1 and 2^N together.

13. The method of claim 12, wherein said multiplication comprises first multiplying the values 2^q2 and 2^q1 together and the multiplication by 2^N is performed by shifting a result of the first multiplication by N bits.

14. The method of claim 9, further comprising the step of converting an initial basis, Z, of the input value, x, to a desired basis, Y, by multiplying the input value, x, by log_Z(Y), where log_Z(Y), is obtained from a look-up table.

15. A digital signal processor for evaluating an x^K function for an input value, x, comprising:

a memory storing at least one look-up table; and

at least one processor, coupled to the memory, operative to;

compute Log(x) in hardware;

multiply said Log(x) value by K; and

determine said x^K function by applying an exponential function in hardware to a result of said multiplying step, wherein one or more of said computation of Log(x) and said exponential function employ at least one look-up table having entries with a fewer number of bits than a number of bits in the input value, x.

16. The digital signal processor of claim 15, where said Log(x) value is obtained by decomposing the input value, x, to a first part, N, a second part, q, and a remaining part, r, wherein the first part, N, is identified by a position of a most significant bit of the input value, x, and the second part, q, is comprised of a number of bits following said most significant bit, wherein said number is small relative to a number of bits in the input value, x.

17. The digital signal processor of claim 16, further comprising the step of obtaining a value

18. The digital signal processor of claim 16, further comprising the step of computing an epsilon term, ε

, using the expression

19. The digital signal processor of claim 18, wherein said epsilon term, ε

, is computed by shifting r by N and multiplying by

20. The digital signal processor of claim 18, further comprising the step of evaluating an expression Log₂(1+ε

) using a polynomial approximation.

21. The digital signal processor of claim 16, wherein said logarithm function is determined for the input value, x, by summing values of N,

22. The digital signal processor of claim 21, further comprising the step of translating an initial basis for said log(x) function to an arbitrary basis, Y, by multiplying a result of said summing step by Log_Y(2), where log_Y(2), is obtained from a look-up table.

23. The digital signal processor of claim 15, where said exponential function of said result is obtained by decomposing the input value, x, to an integer part, N, a first fractional part, q₁, larger than a specified value, x₀, and a second fractional part, q₂, smaller than the specified value, x₀.

24. The digital signal processor of claim 23, wherein a value 2^q2 is computed using a polynomial approximation.

25. The digital signal processor of claim 23, wherein a value 2^q1 is obtained from a look-up table.

26. The digital signal processor of claim 23, wherein said exponential function for said result is obtained by multiplying 2^q2, 2^q1 and 2^N together.

27. The digital signal processor of claim 26, wherein said multiplication comprises first multiplying the values 2^q2 and 2^q1 together and the multiplication by 2^N is performed by shifting a result of the first multiplication by N bits.

28. The digital signal processor of claim 23, further comprising the step of converting an initial basis, Z, of the input value, x, to a desired basis, Y, by multiplying the input value, x, by log_Z(Y), where log_Z(Y), is obtained from a look-up table.

29. An integrated circuit, comprising:

a digital signal processor for evaluating an x^K function for an input value, x, comprising;

a memory storing at least one look-up table; and

at least one processor, coupled to the memory, operative to;

compute Log(x) in hardware;

multiply said Log(x) value by K; and

determine said x^K function by applying an exponential function in hardware to a result of said multiplying step, wherein one or more of said computation of Log(x) and said exponential function employ at least one look-up table having entries with a fewer number of bits than a number of bits in the input value, x.