MEMORY SYSTEM AND INTERLEAVING CONTROL METHOD OF MEMORY SYSTEM

• US 20100199025A1
• Filed: 09/14/2009
• Published: 08/05/2010
• Est. Priority Date: 02/02/2009
• Status: Abandoned Application

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Nanjou, Hiroyuki, Murakami, Tetsuya
• Application Number:
  US12/558,965
• Publication Number:
  US 20100199025A1
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0607 Interleaved addressing
• CPC Class Codes: G06F 2212/7203 Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks

Abstract

A memory system comprising: a plurality of nonvolatile memory areas capable of operating individually; and a memory controller connected to each of the memory areas individually via a ready/busy signal for interleaving an operation in the memory areas by changing a memory area as a target of an operation command, every time the operation command is transmitted, wherein the memory controller includes a priority-level managing unit that manages a level of selection priority for each memory area, so that after transmission of an operation command, the memory controller selects a memory area with a highest level of selection priority from memory areas in a ready state, to change the selected memory area to a target of a next operation command, and shifts the level of selection priority of the selected memory area at a time of next selection to a lowest level by the priority-level managing unit.

Claims

1. A memory system comprising:

a plurality of nonvolatile memory areas capable of operating individually; and

a memory controller connected to each of the memory areas individually via a ready/busy signal for interleaving an operation in the memory areas by changing a memory area as a target of an operation command, every time the operation command is transmitted, wherein

the memory controller includes a priority-level managing unit that manages a level of selection priority for each memory area, so that after transmission of an operation command, the memory controller selects a memory area with a highest level of selection priority from memory areas in a ready state, to change the selected memory area to a target of a next operation command, and shifts the level of selection priority of the selected memory area at a time of next selection to a lowest level by the priority-level managing unit.

2. The memory system according to claim 1, wherein the priority-level managing unit manages the level of selection priority, using an array of identification numbers of each memory area.

3. The memory system according to claim 1, wherein the operation in the memory area includes data write, data read, and data erasure, and the memory area changes a ready/busy signal connected to the memory area itself to a busy state while the operation is being performed, and to a ready state while the operation is not being performed.

4. The memory system according to claim 1, wherein each of the memory areas is a bank constituted by a plurality of NAND flash memories, to which a ready/busy signal is commonly connected.

5. The memory system according to claim 4, wherein

the operation command includes transfer data and a write command sequentially transmitted to a memory area as a target of the operation command,

each of the memory areas further includes a primary buffer that temporarily stores transfer data included in the operation command, a storage area which is a write destination of the transfer data, and a secondary buffer intervening between the primary buffer and the storage area, and wherein

the memory area as a target of the operation command changes a ready/busy signal connected to the memory area itself to a busy state, upon reception of the write command included in the received operation command following the transfer data included in a same operation command, transfers the transfer data stored in the primary buffer to the secondary buffer, writes the transfer data stored in the secondary buffer into the storage area, and changes the ready/busy signal to a ready state upon completion of the write.

6. The memory system according to claim 5, wherein the memory area as a target of the operation command compares the transfer data stored in the secondary buffer with the transfer data written into the storage area, and when both of the transfer data match each other, the memory area changes the ready/busy signal to a ready state, and when both of the transfer data do not match each other, the memory area writes the transfer data stored in the secondary buffer into the storage area again.

7. A memory system comprising:

a plurality of nonvolatile memory areas capable of operating individually; and

a memory controller connected to each of the memory areas individually via a ready/busy signal for interleaving an operation in the memory areas by changing a memory area as a target of an operation command, every time the operation command for performing a plurality of operations is transmitted, wherein

the memory controller includes a priority-level managing unit that manages a level of selection priority for each memory area, and an operation-state recognizing unit that recognizes whether the operation command is being performed based on the ready/busy signal, so that after transmission of the operation command, a memory area with a highest level of selection priority is selected from the memory areas, in which the operation command is not being performed, to change the selected memory area to a next memory area as a target of a next operation command, and shifts the level of selection priority of the selected memory area at a time of next selection to a lowest level by the priority-level managing unit.

8. The memory system according to claim 7, wherein the priority-level managing unit manages the level of selection priority, using an array of identification numbers of each memory area.

9. The memory system according to claim 7, wherein the operation in the memory area includes data write, data read, and data erasure, and the memory area changes a ready/busy signal connected to the memory area itself to a busy state while the operation is being performed, and to a ready state while the operation is not being performed.

10. The memory system according to claim 7, wherein each of the memory areas is a bank constituted by a plurality of NAND flash memories, to which a ready/busy signal is commonly connected.

11. The memory system according to claim 10, wherein the memory area includes n planes capable of performing a different operation respectively, and the operation command causes the n planes included in the memory area to execute a different operation respectively.

12. The memory system according to claim 11, wherein the operation command includes n pairs of transfer data and write command designating a different plane as a write destination respectively, and sequentially transmitted to a memory area as a target of the operation command,

each of the planes included in the memory area further includes a primary buffer that temporarily stores transfer data designating the plane itself as a write destination and included in the operation command, a storage area which is a write destination of the transfer data, and a secondary buffer intervening between the primary buffer and the storage area,

the memory area as a target of the operation command changes a ready/busy signal connected to the memory area itself to a busy state only for a predetermined time, upon reception of the write command included in the operation command, changes the ready/busy signal to a busy state upon reception of a last write command of the write commands included in the operation command, transfers the transfer data stored in the primary buffer of each of the plane to the secondary buffer of each of the plane, writes the transfer data stored in the secondary buffer into the storage area of each of the plane, and changes the ready/busy signal to a ready state upon completion of the write in each of the plane.

13. The memory system according to claim 12, wherein the memory area as a target of the operation command compares the transfer data stored in the secondary buffer with the transfer data written into the storage area for each plane, and when both of the transfer data match each other in all the planes included in the memory area itself, the memory area changes the ready/busy signal to a ready state, and when there is a plane in which both of the transfer data do not match each other, the memory area writes the transfer data stored in the secondary buffer of the plane into the storage area again.

14. The memory system according to claim 12, wherein after transmission of the operation command to the memory area as a target of the operation command, the operation-state recognizing unit recognizes that the memory area as a target of the operation command is performing the operation command in a time between a first change of n changes to a busy state and a last return of n returns to a ready state.

15. An interleaving control method of a memory system for changing a memory area as a target of an operation command every time the operation command is transmitted to a plurality of nonvolatile memory areas capable of individually operating and individually outputting a ready/busy signal, thereby interleaving an operation in the memory areas, the method comprising:

selecting a memory area with a highest level of selection priority from the memory areas in a ready state based on a level of selection priority of each memory area set beforehand, to designate the selected memory area as a memory area as a target of the operation command;

transmitting the operation command to the memory area as the target of the operation command; and

shifting the level of selection priority of the selected memory area at a time of next selection to a lowest level.

16. The interleaving control method of a memory system according to claim 15, wherein the operation of the memory area includes data write, data read, and data erasure, and the memory area changes a ready/busy signal connected to the memory area itself to a busy state while the operation is being performed, and to a ready state while the operation is not being performed.

17. The interleaving control method of a memory system according to claim 15, wherein each of the memory areas is a bank constituted by a plurality of NAND flash memories, to which a ready/busy signal is commonly connected.