Systems and Methods for Storing and Recovering Controller Data in Non-Volatile Memory Devices

• US 20100199125A1
• Filed: 02/04/2009
• Published: 08/05/2010
• Est. Priority Date: 02/04/2009
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Reche, Cory
• Granted Patent: US 8,645,749 B2
• Time in Patent Office: Days
• US Class Current: 714/6.22
• CPC Class Codes: G06F 11/108 Parity data distribution in semiconductor storages, e.g. in SSD
• CPC Class Codes: G06F 2211/1057 Parity-multiple bits-RAID6, i.e. RAID 6 implementations
• CPC Class Codes: G06F 2211/1059 Parity-single bit-RAID5, i.e. RAID 5 implementations
• CPC Class Codes: G06F 2211/1061 Parity-single bit-RAID4, i.e. RAID 4 implementations

Abstract

Systems and methods are disclosed for storing the firmware and other data of a flash memory controller, such as using a RAID configuration across multiple flash memory devices or portions of a single memory device. In various embodiments, the firmware and other data used by a controller, and error correction information, such as parity information for RAID configuration, may be stored across multiple flash memory devices, multiple planes of a multi-plane flash memory device, or across multiple blocks or pages of a single flash memory device. The controller may detect the failure of a memory device or a portion thereof, and reconstruct the firmware and/or other data from the other memory devices or portions thereof.

Claims

1. A method of operating at least one non-volatile memory device, comprising:

storing portions of at least one of a program executable by a controller or operating data associated with a program executable by the controller across multiple memory devices or multiple portions of the memory device; and

storing error correction information associated with the at least one of a program executable by a controller or operating data associated with a program executable by a controller across multiple memory devices or multiple portions of a memory device, wherein in the event of a respective failure of one of the memory devices or one of the portions of the memory device, the controller can recover the at least one of a program executable by the controller or operating data associated with a program executable by the controller.

2. The method of claim 1, wherein the at least one of a program comprises firmware for the controller, wherein the controller is configured to control the multiple memory devices or the memory device.

3. The method of claim 1, wherein storing the portions of the at least one of a program comprises dividing the program across multiple memory devices or multiple portions of the memory device.

4. The method of claim 1, wherein storing the error correction information comprises storing parity information across multiple memory devices or multiple portions of a memory device.

5. The method of claim 1, wherein the multiple portions comprise multiple planes of a memory device.

6. The method of claim 1, wherein the multiple portions comprise multiple blocks of a memory device.

7. The method of claim 1, wherein the multiple portions comprise multiple pages of a memory device.

8. A method of operating at least one non-volatile memory device, comprising:

detecting a failure of one or more portions of the at least one memory device; and

restoring portions of at least one of a program executable by a controller coupled to the memory device or operating data associated with a program executable by the controller from multiple functioning portions of the memory device.

9. The method of claim 8, wherein the one or more portions comprise one or more blocks, planes, or pages of the memory device.

10. The method of claim 8, comprising reading error correction information from multiple functioning portions of the memory device.

11. The method of claim 8, wherein restoring portions comprises restoring the at least one of a program executable by a controller coupled to the memory device or operating data associated with a program executable by the controller using the error correction information.

12. The method of claim 8, comprising operating the controller with the restored portions of the at least one of a program executable by a controller coupled to the memory device or operating data associated with a program executable by the controller.

13. A system, comprising:

a non-volatile memory device; and

a memory controller coupled to the memory device and configured to store portions of at least one of a program executable by a controller or operating data associated with a program executable by the controller across multiple memory devices or multiple portions of a memory device.

14. The system of claim 13, wherein the memory device comprises a NAND memory device.

15. The system of claim 13, wherein the memory controller comprises control logic and RAID logic.

16. The system of claim 13, wherein the memory device comprises a multi-plane device and the controller is configured to store the portions of the at least one of a program executable by a controller or operating data associated with a program executable by the controller across multiple planes of the memory device.

17. The system of claim 13, wherein the memory device comprises a plurality of blocks and the controller is configured to store the portions of the at least one of a program executable by a controller or operating data associated with a program executable by the controller across multiple blocks of the memory device.

18. The system of claim 13, wherein the memory device comprises a plurality of pages and the controller is configured to store the program executable by a controller or operating data associated with a program executable by the controller across multiple pages of the memory device.

19. A system comprising;

a non-volatile memory device;

a memory controller coupled to the device; and

firmware stored on the memory controller and configured to operate the memory device, wherein the firmware is divided and stored across multiple portions of the memory device.

20. The system of claim 19, wherein the multiple portions comprise pages of the memory device.

21. The system of claim 19, wherein the multiple portions comprise blocks of the memory device.

22. The system of claim 19, wherein the multiple portions comprise planes of the memory device.

23. The method of claim 19, wherein the memory controller comprises a RAID controller.

24. A method of operating a memory device, comprising:

storing firmware of the device across multiple portions of the device such the firmware and error correction information is divided and stored across on the portions.

25. The method of claim 24, wherein the multiple portions comprise a block of the memory device.

26. The method of claim 24, wherein the multiple portions comprise a page of the memory device.