METHOD AND APPARATUS FOR PERFORMING RLC MODELING AND EXTRACTION FOR THREE-DIMENSIONAL INTEGRATED CIRCUIT (3D-IC) DESIGNS

• US 20100199236A1
• Filed: 01/30/2009
• Published: 08/05/2010
• Est. Priority Date: 01/30/2009
• Status: Active Grant

• Current Assignee: Synopsys Incorporated
• Original Assignee: Synopsys Incorporated
• Inventors: Hu, Xiaoping, Biswas, Baribrata, Qiu, Beifang, Chen, Qiushi, Koshy, Mathew, Chiang, Charles C.
• Granted Patent: US 8,146,032 B2
• Time in Patent Office: Days
• US Class Current: 716/103
• CPC Class Codes: G06F 30/367 Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05 of an individual bonding area
• CPC Class Codes: H01L 2224/13 of an individual bump connector
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/16146 the bump connector connecting to a via connection in the semiconductor or solid-state body
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 2225/06572 Auxiliary carrier between devices, the carrier having an electrical connection structure
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/552 Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 25/0652 the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/0655 the devices being arranged next to each other
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 2924/15192 Resurf arrangement of the internal vias

Abstract

One embodiment of the present invention provides a system that performs an RLC extraction for a three-dimensional integrated circuit (3D-IC) die. During operation, the system receives a 3D-IC die description. The system then transforms the 3D-IC die description into a set of 2D-IC die descriptions, wherein the transform maintains equivalency between the set of 2D-IC die descriptions and the 3D-IC die description. Next, for each 2D-IC die description in the set of 2D-IC die descriptions, the system performs an electrical property extraction using a 2D-IC extraction tool to obtain a 2D-IC RLC netlist file. The system then combines the set of 2D-IC RLC netlist files for the set of 2D-IC die descriptions to form an RLC netlist file for the 3D-IC die description.

Claims

1. A method for performing an RLC extraction for a three-dimensional integrated circuit (3D-IC) die, the method comprising:

receiving a 3D-IC die description;

transforming the 3D-IC die description into a set of 2D-IC die descriptions, wherein the transform maintains equivalency between the set of 2D-IC die descriptions and the 3D-IC die description;

for each 2D-IC die description in the set of 2D-IC die descriptions, performing an electrical property extraction using a 2D-IC extraction tool to obtain a 2D-IC RLC netlist file; and

combining the set of 2D-IC RLC netlist files for the set of 2D-IC die descriptions to form an RLC netlist file for the 3D-IC die description.

2. The method of claim 1, wherein the 3D-IC die description comprises a through-silicon via (TSV) die, wherein the TSV die further includes:

a front-side layer stack which includes a top metal layer;

a back-side layer stack which includes at least one back-side metal layer;

a double-sided substrate which is disposed between the front-side layer stack and the back-side layer stack; and

a TSV which passes through the double-sided substrate, and which electrically couples the front-side layer stack with the back-side layer stack.

3. The method of claim 2, wherein transforming the 3D-IC die description into a set of 2D-IC die descriptions involves transforming the TSV die into one or more 2D-IC die descriptions.

4. The method of claim 3, wherein transforming the TSV die into one or more 2D-IC die descriptions involves:

projecting the back-side layer stack onto the top of the front-side layer stack of the TSV die to create a virtual front-side layer stack, thereby removing the back-side layer stack, thereby transforming the double-sided substrate into a single-sided substrate; and

coupling the TSV to the virtual front-side layer stack while decoupling the TSV from the single-sided substrate, thereby transforming the TSV die into a 2D-IC die description.

5. The method of claim 3, wherein transforming the TSV die into one or more 2D-IC die descriptions further involves maintaining equivalency between the TSV die and the 2D-IC die description by creating a virtual substrate shield layer which is a conductor layer disposed between the virtual front-side layer stack and the top metal layer of the front-side layer stack, wherein the TSV passes through the virtual substrate shield layer.

6. The method of claim 5, wherein the virtual substrate shield layer is invisible to the front-side layer stack.

7. The method of claim 1, wherein the 3D-IC die description comprises a die stack, wherein the die stack further includes:

a first die;

a second die adjacent to the first die; and

a TSV interconnecting the first die and the second die.

8. The method of claim 7, wherein transforming the 3D-IC die description into the set of 2D-IC die descriptions involves transforming the die stack into at least two separate dies.

9. The method of claim 8, wherein transforming the die stack into at least two separate dies involves:

identifying a transform boundary between the first die and the second die; and

separating the first die from the second die to create a first transformed die and a second transformed die, respectively,

wherein the first transformed die includes the first die and at least one metal layer adjacent to the transform boundary in the second die;

wherein the second transformed die includes the second die and at least one metal layer adjacent to the transform boundary in the first die; and

wherein including at least one metal layer from an adjacent die facilitates maintaining equivalency between the two transformed dies and the die stack.

10. The method of claim 9, wherein the transform boundary can be:

an interface between a top metal layer in the first die and a top metal layer in the second die in a face-to-face configuration of the 3D-IC die description;

an interface between a back-side metal layer in the first die and a top metal layer in the second die in a face-to-back configuration of the 3D-IC die description;

or

an interface between a back-side metal layer in the first die and a back-side metal layer in the second die in a back-to-back configuration of the 3D-IC die description.

11. The method of claim 9, wherein the first die is a TSV die.

12. The method of claim 9, wherein the method further comprises transforming each of the transformed dies into one or more 2D-IC die descriptions.

13. The method of claim 1, wherein the equivalency between the set of 2D-IC die descriptions and the 3D-IC die description can include:

an electrical property equivalency; and

a connectivity equivalency.

14. The method of claim 1, wherein the TSV die includes a silicon-interposer die.

15. A computer-readable storage medium storing instructions that when executed by a computer cause the computer to perform a method for performing an RLC extraction for a three-dimensional integrated circuit (3D-IC) die, the method comprising:

receiving a 3D-IC die description;

transforming the 3D-IC die description into a set of 2D-IC die descriptions, wherein the transform maintains equivalency between the set of 2D-IC die descriptions and the 3D-IC die description;

for each 2D-IC die description in the set of 2D-IC die descriptions, performing an electrical property extraction using a 2D-IC extraction tool to obtain a 2D-IC RLC netlist file; and

combining the set of 2D-IC RLC netlist files for the set of 2D-IC die descriptions to form an RLC netlist file for the 3D-IC die description.

16. The computer-readable storage medium of claim 15, wherein the 3D-IC die description comprises a through-silicon via (TSV) die, wherein the TSV die further includes:

a front-side layer stack which includes a top metal layer;

a back-side layer stack which includes at least one back-side metal layer;

a double-sided substrate which is disposed between the front-side layer stack and the back-side layer stack; and

a TSV which passes through the double-sided substrate, and which electrically couples the front-side layer stack with the back-side layer stack.

17. The computer-readable storage medium of claim 16, wherein transforming the 3D-IC die description into a set of 2D-IC die descriptions involves transforming the TSV die into one or more 2D-IC die descriptions.

18. The computer-readable storage medium of claim 17, wherein transforming the TSV die into one or more 2D-IC die descriptions involves:

projecting the back-side layer stack onto the top of the front-side layer stack of the TSV die to create a virtual front-side layer stack, thereby removing the back-side layer stack, thereby transforming the double-sided substrate into a single-sided substrate; and

coupling the TSV to the virtual front-side layer stack while decoupling the TSV from the single-sided substrate, thereby transforming the TSV die into a 2D-IC die description.

19. The computer-readable storage medium of claim 17, wherein transforming the TSV die into one or more 2D-IC die descriptions further involves maintaining equivalency between the TSV die and the 2D-IC die description by creating a virtual substrate shield layer which is a conductor layer disposed between the virtual front-side layer stack and the top metal layer of the front-side layer stack, wherein the TSV passes through the virtual substrate shield layer.

20. The computer-readable storage medium of claim 19, wherein the virtual substrate shield layer is invisible to the front-side layer stack.

21. The computer-readable storage medium of claim 15, wherein the 3D-IC die description comprises a die stack, wherein the die stack further includes:

a first die;

a second die adjacent to the first die; and

a TSV interconnecting the first die and the second die.

22. The computer-readable storage medium of claim 21, wherein transforming the 3D-IC die description into the set of 2D-IC die descriptions involves transforming the die stack into at least two separate dies.

23. The computer-readable storage medium of claim 22, wherein transforming the die stack into at least two separate dies involves:

identifying a transform boundary between the first die and the second die; and

separating the first die from the second die to create a first transformed die and a second transformed die, respectively,

wherein the first transformed die includes the first die and at least one metal layer adjacent to the transform boundary in the second die;

wherein the second transformed die includes the second die and at least one metal layer adjacent to the transform boundary in the first die; and

wherein including at least one metal layer from an adjacent die facilitates maintaining equivalency between the two transformed dies and the die stack.

24. The computer-readable storage medium of claim 23, wherein the transform boundary can be:

an interface between a top metal layer in the first die and a top metal layer in the second die in a face-to-face configuration of the 3D-IC die description;

an interface between a back-side metal layer in the first die and a top metal layer in the second die in a face-to-back configuration of the 3D-IC die description;

or

an interface between a back-side metal layer in the first die and a back-side metal layer in the second die in a back-to-back configuration of the 3D-IC die description.

25. The computer-readable storage medium of claim 23, wherein the first die is a TSV die.

26. The computer-readable storage medium of claim 23, wherein the method further comprises transforming each of the transformed dies into one or more 2D-IC die descriptions.

27. The computer-readable storage medium of claim 15, wherein the equivalency between the set of 2D-IC die descriptions and the 3D-IC die description can include:

an electrical property equivalency; and

a connectivity equivalency.

28. The computer-readable storage medium of claim 16, wherein the TSV die includes a silicon-interposer die.

29. An apparatus that performs an RLC extraction for a three-dimensional integrated circuit (3D-IC) die, comprising:

a processor;

a memory;

a receiving mechanism configured to receive a 3D-IC die description;

a transforming mechanism configured to transform the 3D-IC die description into a set of 2D-IC die descriptions, wherein the transform maintains equivalency between the set of 2D-IC die descriptions and the 3D-IC die description;

a 2D-IC extraction tool configured to perform an electrical property extraction for each 2D-IC die description in the set of 2D-IC die descriptions to obtain a 2D-IC RLC netlist file; and

a combining mechanism configured to combine the set of 2D-IC RLC netlist files for the set of 2D-IC die descriptions to form an RLC netlist file for the 3D-IC die description.