Parallel Electronic Design Automation: Shared Simultaneous Editing

• US 20100199240A1
• Filed: 04/06/2010
• Published: 08/05/2010
• Est. Priority Date: 12/10/2001
• Status: Active Grant

• Current Assignee: Siemens Industry Software Inc. (Siemens AG)
• Original Assignee: Mentor Graphics Corporation (Siemens AG)
• Inventors: Natarajan, Venkat, Potts, Henry, Smith, Edwin Franklin, Petunin, Vladimir, Pfeil, Charles
• Granted Patent: US 7,949,990 B2
• Time in Patent Office: Days
• US Class Current: 716/137
• CPC Class Codes: G06F 2111/12 Symbolic schematics
• CPC Class Codes: G06F 2115/12 Printed circuit boards [PCB] or multi-chip modules [MCM]
• CPC Class Codes: G06F 30/00 Computer-aided design [CAD]
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347

Abstract

A method to simultaneously allow multiple users to edit in shared areas of a master design includes displaying the master design, allowing a first user to edit in a shared area of the design, while simultaneously allowing a second user to edit in a shared area of the design while preserving the integrity of the design.

Claims

1. A method comprising

maintaining a master printed circuit board design on a server computer;

displaying at least a portion of the master printed circuit board design to a user on a client computer;

receiving an edit command to edit the master printed circuit board design at the client computer;

executing the edit command on the client computer to produce an edit for the master printed circuit board design; and

providing the edit to the server computer to implement in the master printed circuit board design.

2. The method recited in claim 1, further comprising

determining if the edit will create an error in the master printed circuit board design;

and

if it is determined that the edit will not create an error in the master printed circuit board design, then making the edit to the master circuit design.

3. A method comprising

maintaining a master circuit design on a server computer;

displaying at least a portion of the master circuit design to a user on a client computer;

receiving an edit command to edit the master circuit design at the client computer;

determining at the client computer if the edit will create an error in the master circuit design; and

determining at the server computer if the edit will create an error in the master circuit design.

4. The method recited in claim 3, further comprising:

if it is determined at the client computer that the edit will not create an error in the master circuit design; and

if it is determined at the server computer that the edit will create an error in the master circuit design;

then making the edit to the master circuit design.

5. The method recited in claim 3, further comprising:

executing the edit command on the client computer to produce an edit change for the master circuit design;

determining at the client computer if the edit change will create an error in the master circuit design;

providing the edit change to the server computer to implement in the master circuit design; and

determining at the server computer if the edit change will create an error in the master circuit design.