Process For Through Silicon Via Filling

• US 20100200412A1
• Filed: 04/16/2010
• Published: 08/12/2010
• Est. Priority Date: 08/18/2008
• Status: Active Grant

• Current Assignee: Novellus Systems Incorporated (Lam Research Corporation)
• Original Assignee: Novellus Systems Incorporated (Lam Research Corporation)
• Inventors: Reid, Jonathan D., Wang, Katie Qun, Wiley, Mark J.
• Granted Patent: US 8,043,967 B2
• Time in Patent Office: Days
• US Class Current: 205/123
• CPC Class Codes: C25D 17/001 Apparatus specially adapted for electrolytic coating of wafers, e.g. semiconductors or solar cells
• CPC Class Codes: C25D 21/12 Process control or regulation controlling or regulating in general G05
• CPC Class Codes: C25D 3/38 of copper
• CPC Class Codes: C25D 7/123 Semiconductors first coated with a seed layer or a conductive layer
• CPC Class Codes: H01L 21/2885 using an external electrical current, i.e. electro-deposition
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/0554 External layer
• CPC Class Codes: H01L 2224/0555 Shape
• CPC Class Codes: H01L 2224/0556 Disposition
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/13025 the bump connector being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details

Abstract

A semiconductor electroplating process deposits copper into the through silicon via hole to completely fill the through silicon via in a substantially void free is disclosed. The through silicon via may be more than about 3 micrometers in diameter and more that about 20 micrometers deep. High copper concentration and low acidity electroplating solution is used for deposition copper into the through silicon vias.

Claims

1. A method of plating a through silicon via for connecting at least two integrated circuits, wherein the through silicon via has a diameter of at least about 3 micrometers and a depth of at least about 20 micrometers, the method comprising:

contacting a structure having a through silicon via hole with a plating solution having copper ions at a concentration of at least about 40 grams per liter and chloride ions at a concentration of no greater than about 2 ppm; and

while contacting the structure, plating copper into the through silicon via hole to completely fill the through silicon via hole in a substantially void free manner,

wherein a deposition rate during the plating is higher at the bottom of the through silicon via hole than near the opening of the through silicon via hole.

2. The method of claim 1, wherein the through silicon via is completely filled in less than about 20 minutes.

3. The method of claim 1, wherein the through silicon via has a diameter of between about 3 and 100 micrometers and a depth of between about 20 and 200 micrometers.

4. The method of claim 1, wherein the through silicon via has a diameter of between about 5 and 20 micrometers and a depth of between about 40 and 150 micrometers.

5. The method of claim 1, wherein the through silicon via has an aspect ratio of between about 3:

1 to 10;

1.

6. The method of claim 1, wherein the concentration of the copper ions in the plating solution is between about 40 grams per liter and 200 grams per liter.

7. The method of claim 1, wherein the concentration of the copper ions in the plating solution is between about 60 grams per liter and 100 grams per liter.

8. The method of claim 1, wherein the plating solution further comprises an oxidizing agent and wherein the oxidizing agent oxidizes the plated copper on a wafer field at a rate of between about 200 Å

/minute and 3000 Å

/minute when a current is not applied to the wafer.

9. The method of claim 8, wherein the oxidizing agent comprises a hydrogen peroxide solution.

10. The method of claim 9, wherein the hydrogen peroxide solution comprises 30% hydrogen peroxide by weight and the concentration of the hydrogen peroxide solution in the plating solution is between about 0.0025 ml per liter and 50 ml per liter.

11. The method of claim 8, wherein the oxidizing agent comprises elemental oxygen.

12. The method of claim 11, wherein the concentration of the elemental oxygen is between about 1 mg per liter and 20 mg per liter.

13. The method of claim 12, wherein the concentration of the elemental oxygen is between about 1 mg per liter and 5 mg per liter.

14. The method of claim 8, wherein the oxidizing agent comprises cerium ions.

15. The method of claim 8 wherein the oxidizing agent comprises iron ions.

16. The method of claim 15, wherein the concentrations of the iron ions in different oxidation states are in equilibrium and wherein such equilibrium is maintained by reaction at an inert anode.

17. The method of claim 8, wherein the plating solution further comprising a reducing agent, wherein the reducing agent has a concentration gradient in the through silicon via hole and wherein the reducing agent impacts oxidation of the copper.

18. The method of claim 1, wherein a source of the copper ions comprises a copper salt selected from the group consisting of copper methane sulfonate, copper sulfate, copper pyrophosphate, copper propanesulfonate, and combination of thereof.

19. The method of claim 1, wherein the copper ions have a transference number of at least about 0.2 in the plating solution while plating copper into the through silicon via hole.

20. The method of claim 1, wherein the copper ions have a transference number of at least about 0.4 in the plating solution while plating copper into the through silicon via hole.

21. The method of claim 1, wherein the plating solution is maintained at a temperature of between about 40°

C. and 75°

C. for at least a fraction of the time while plating copper into the through silicon via hole.

22. The method of claim 1, wherein the plating solution is maintained at least about a room temperature for at least a fraction of the time while plating copper into the through silicon via hole.

23. The method of claim 1, wherein there is substantially no net deposition of copper onto field regions of the structure between a plurality of through silicon via holes while plating copper.

24. The method of claim 1, wherein the plating solution is substantially free of chloride ions.

25. The method of claim 1, further comprising pretreating a seed layer deposited onto the structure prior to the plating.

26. The method of claim 25, wherein the pretreating is performed using one or more liquids selected from the group consisting of water, a dilute acidic solution, a dilute basic solution, a surfactant containing solution, and the plating solution.

27. The method of claim 1, wherein the structure is a wafer on which at least one of the integrated circuits is fabricated.

28. The method of claim 1, wherein the plating solution has a pH of between about 2 and 6.

29. A method of plating a through silicon via for connecting at least two integrated circuits, wherein the through silicon via has a diameter of at least about 3 micrometers and a depth of at least about 20 micrometers, the method comprising:

pretreating a seed layer deposited onto a structure;

contacting the structure having a through silicon via hole with a plating solution having a copper ions at a concentration of between about 60 gram per liter and 100 gram per liter and chloride ions at a concentration of no greater than about 2 ppm; and

while contacting the structure, plating copper into the through silicon via hole to completely fill the through silicon via hole in a substantially void free manner,

wherein there is substantially no net deposition of copper onto field regions of the structure between a plurality of through silicon via holes while plating copper, and wherein a deposition rate during the plating is higher at the bottom of the through silicon via hole than near the opening of the through silicon via hole.

30. A copper plating solution for depositing copper in a through silicon via for connecting at least two integrated circuits, wherein the through silicon via has a diameter of at least about 3 micrometers and a depth of at least about 20 micrometers, the copper plating solution comprising:

copper ions at a concentration of between about 60 grams per liter and 100 grams per liter;

sulfuric acid; and

chloride ions at a concentration of no greater than about 2 ppm.