TRANSISTOR AND METHOD OF MANUFACTURING THE SAME

• US 20100200897A1
• Filed: 08/27/2008
• Published: 08/12/2010
• Est. Priority Date: 09/05/2007
• Status: Abandoned Application

• Current Assignee: NXP B.V. (NXP Semiconductors NV)
• Original Assignee: NXP B.V. (NXP Semiconductors NV)
• Inventors: Duffy, Raymond, Heringa, Anco, Meunier-Beillard, Philippe
• Application Number:
  US12/676,007
• Publication Number:
  US 20100200897A1
• Time in Patent Office: Days
• US Class Current: 257/288
• CPC Class Codes: H01L 21/2652 Through-implantation
• CPC Class Codes: H01L 21/266 using masks H01L21/26586 takes precedence
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/6653 using the removal of at least part of spacer, e.g. disposable spacer
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/66598 forming drain [D] and lightly doped drain [LDD] simultaneously, e.g. using implantation through the wings a T-shaped layer, or through a specially shaped layer

Abstract

A method of manufacturing a transistor (400), the method comprising forming a gate (101) on a substrate (102), forming a spacer (201) on lateral side walls of the gate (101) and on an adjacent portion (202) of the substrate (102), rearranging material of the spacer (201) so that the rearranged spacer (301) covers only a lower portion (303) of the lateral side walls of the gate (101) and an increased portion (302) of the substrate (102), and providing source/drain regions (402, 403) in a portion of the substrate (102) below the rearranged spacer (301).

Claims

1. A method of manufacturing a transistor, the method comprising:

forming a gate on a substrate;

forming a spacer on lateral side walls of the gate and on an adjacent portion of the substrate;

rearranging material of the spacer such that the rearranged spacer covers only a lower portion of the lateral side walls of the gate and an increased portion of the substrate;

providing source/drain regions in a portion of the substrate below the rearranged spacer.

2. The method of claim 1, comprising implanting the source/drain regions in the portion of the substrate below the rearranged spacer.

3. The method of claim 1, comprising rearranging the material of the spacer by annealing.

4. The method of claim 1, comprising rearranging the material of the spacer in such a manner that a thickness of the rearranged spacer gradually increases towards the gate.

5. The method of claim 1, comprising removing the rearranged spacer after providing the source/drain regions in the portion of the substrate below the rearranged spacer.

6. The method of claim 1, comprising forming a protection structure, particularly a protection structure being essentially L-shaped in a cross-sectional view, between the gate the spacer.

7. The method of claim 1, comprising forming the spacer on the lateral side walls of the gate and on the adjacent portion of the substrate by

depositing spacer material over the gate and the substrate;

and

removing part of the spacer material so that the spacer remains only on the lateral side walls of the gate and on the adjacent portion of the substrate.

13. The method of claim 3, wherein the annealing is hydrogen annealing.

8. A transistor, the transistor comprising

a substrate;

a gate on the substrate;

a concave spacer which covers only a lower portion of lateral side walls of the gate and a portion of the substrate;

source/drain regions in a portion of the substrate below the concave spacer.

9. The transistor of claim 8, wherein the spacer comprises a material of the group consisting of silicon-germanium, a polymer, silicon, silicon oxide, and silicon nitride.

10. The transistor of claim 8, wherein the source/drain regions in the portion of the substrate below the spacer have a gradually decreasing depth towards the gate.

11. The transistor of claim 8, comprising a further spacer on a lateral wall of the gate, essentially above the spacer, and having a thickness smaller than a thickness of the spacer.

12. The transistor of claim 11, wherein the further spacer is a convex spacer.