IMAGE AND LIGHT SENSOR CHIP PACKAGES
First Claim
1. A light sensor chip comprising:
- a semiconductor substrate;
multiple transistors each including a diffusion or doped area in said semiconductor substrate and a gate over a top surface of said semiconductor substrate;
a first dielectric layer over said top surface of said semiconductor substrate;
an interconnection layer over said first dielectric layer;
a second dielectric layer over said interconnection layer and over said first dielectric layer;
a metal trace over said second dielectric layer, wherein said metal trace has a width smaller than 1 micrometer;
an insulating layer on a first region of said metal trace, over said interconnection layer and over said first and second dielectric layers, wherein an opening in said insulating layer is over a second region of said metal trace, and said second region is at a bottom of said opening;
a polymer layer on said insulating layer;
a metal layer on said second region of said metal trace, wherein said metal layer includes a portion in said polymer layer, wherein said metal layer is connected to said second region of said metal trace through said opening, wherein said metal layer has a thickness between 3 and 100 micrometers and a width between 5 and 100 micrometers; and
a transparent substrate on a top surface of said polymer layer and over said multiple transistors, wherein an air space is between said insulating layer and said transparent substrate and over said multiple transistors, wherein a bottom surface of said transparent substrate provides a top wall of said air space, and said polymer layer provides a sidewall of said air space.
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0 Petitions
Accused Products
Abstract
An image or light sensor chip package includes an image or light sensor chip having a non-photosensitive area and a photosensitive area surrounded by the non-photosensitive area. In the photosensitive area, there are light sensors, a layer of optical or color filter array over the light sensors and microlenses over the layer of optical or color filter array. In the non-photosensitive area, there are an adhesive polymer layer and multiple metal structures having a portion in the adhesive polymer layer. A transparent substrate is formed on a top surface of the adhesive polymer layer and over the microlenses. The image or light sensor chip package also includes wirebonded wires or a flexible substrate bonded with the metal structures of the image or light sensor chip.
158 Citations
20 Claims
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1. A light sensor chip comprising:
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a semiconductor substrate; multiple transistors each including a diffusion or doped area in said semiconductor substrate and a gate over a top surface of said semiconductor substrate; a first dielectric layer over said top surface of said semiconductor substrate; an interconnection layer over said first dielectric layer; a second dielectric layer over said interconnection layer and over said first dielectric layer; a metal trace over said second dielectric layer, wherein said metal trace has a width smaller than 1 micrometer; an insulating layer on a first region of said metal trace, over said interconnection layer and over said first and second dielectric layers, wherein an opening in said insulating layer is over a second region of said metal trace, and said second region is at a bottom of said opening; a polymer layer on said insulating layer; a metal layer on said second region of said metal trace, wherein said metal layer includes a portion in said polymer layer, wherein said metal layer is connected to said second region of said metal trace through said opening, wherein said metal layer has a thickness between 3 and 100 micrometers and a width between 5 and 100 micrometers; and a transparent substrate on a top surface of said polymer layer and over said multiple transistors, wherein an air space is between said insulating layer and said transparent substrate and over said multiple transistors, wherein a bottom surface of said transparent substrate provides a top wall of said air space, and said polymer layer provides a sidewall of said air space. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A light sensor chip comprising:
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a semiconductor substrate; multiple transistors each including a diffusion or doped area in said semiconductor substrate and a gate over a top surface of said semiconductor substrate; a first dielectric layer over said top surface of said semiconductor substrate; an interconnection layer over said first dielectric layer; a second dielectric layer over said interconnection layer and over said first dielectric layer; a metal trace over said second dielectric layer, wherein said metal trace has a width smaller than 1 micrometer; an insulating layer on a first region of said metal trace, over said interconnection layer and over said first and second dielectric layers, wherein an opening in said insulating layer is over a second region of said metal trace, and said second region is at a bottom of said opening; a metal layer on said second region of said metal trace, wherein said metal layer is connected to said second region of said metal trace through said opening, wherein said metal layer has a thickness between 3 and 100 micrometers and a width between 5 and 100 micrometers; a polymer layer under a bottom surface of said semiconductor substrate; and a transparent substrate on a bottom surface of said polymer layer, under said bottom surface of said semiconductor substrate and under multiple transistors, wherein an air space is between said semiconductor substrate and said transparent substrate and under said multiple transistors, wherein a top surface of said transparent substrate provides a bottom wall of said air space, and said polymer layer provides a sidewall of said air space. - View Dependent Claims (8, 9, 10, 11, 12, 13)
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14. A light sensor chip comprising:
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a semiconductor substrate having a thickness between 3 and 50 micrometers, wherein a through via is in said semiconductor substrate, wherein said semiconductor substrate has a bottom surface at a horizontal level; multiple transistors each including a diffusion or doped area in said semiconductor substrate and a gate over a top surface of said semiconductor substrate; a dielectric layer over said top surface of said semiconductor substrate; a metal trace over said dielectric layer, wherein said metal trace has a width smaller than 1 micrometer; a passivation layer over said metal trace and over said dielectric layer; a metal layer having a first portion in said through via, wherein a bottom surface of said metal layer is lower than said horizontal level; a polymer layer under said bottom surface of said semiconductor substrate; and a transparent substrate on a bottom surface of said polymer layer, under said bottom surface of said semiconductor substrate and under multiple transistors, wherein an air space is between said semiconductor substrate and said transparent substrate and under said multiple transistors, wherein a top surface of said transparent substrate provides a bottom wall of said air space, and said polymer layer provides a sidewall of said air space. - View Dependent Claims (15, 16, 17, 18, 19, 20)
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Specification