Mosfets with terrace irench gate and improved source-body contact

• US 20100200912A1
• Filed: 02/11/2009
• Published: 08/12/2010
• Est. Priority Date: 02/11/2009
• Status: Abandoned Application

• Current Assignee: Force Mos Technology Co., Ltd.
• Original Assignee: Force Mos Technology Co., Ltd.
• Inventors: Hsieh, Fu-Yuan
• Application Number:
  US12/379,012
• Publication Number:
  US 20100200912A1
• Time in Patent Office: Days
• US Class Current: 257/329
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A trench MOSFET with terrace gates and improved source-body contact structure is disclosed. When refilling the gate trenches, the deposited polysilicon layer is higher than the sidewalls of the trenches to be used as terrace gates of the MOSFET, and the improved source-body contact structure can enlarge the P+ area below to wrap the sidewalls and bottom of source-body contact within P body region to further enhance the avalanche capability.

Claims

1. A vertical semiconductor power MOS device comprising a plurality of semiconductor power cells with each cell comprising a plurality of trench gates surrounded by source regions encompassed in body regions above a drain region disposed on a bottom surface of a substrate, wherein said trench MOSFET further comprising:

a substrate of a first type conductivity;

an epitaxial layer of said first type conductivity over said substrate, having a lower doping concentration than said substrate;

a plurality of trenches extending into said epitaxial layer, surrounded by a plurality of source regions of said first type conductivity above said body regions of the second type conductivity;

a first insulation layer lining said trenches as gate dielectric;

a plurality of terrace gates made of doped polysilicon over said first insulation layer with top surface higher than front surface of said epitaxial layer;

a second insulation layer disposed over said epitaxial layer and covering the outer surface of said terrace gates to isolate source metal which contacts to said both source and body region, from said doped polysilicon as said terrace gate regions;

at least one source-body contact trench opened with sidewalls substantially perpendicular to a top epitaxial surface within source regions, and with tapered sidewalls respecting to said top surface into said body regions;

a heavily doped area of said second conductivity type around the sidewalls and bottom of said source-body contact trench within said body region;

a source-body contact metal plug deposited over a barrier layer to connect said source region and said body region to front source metal;

a front metal disposed on front surface of device as source metal;

a backside metal disposed on backside of said substrate as drain metal.

2. The trench MOSFET of claim 1, wherein the width of top portion of source-body contact is larger than lower portion within said second insulation layer;

3. The trench MOSFET of claim 1, wherein the angle between said source-body contact trench sidewalls and said top surface is 90±

5 degree within said source regions and is less than 85 degree within said body region.

4. The trench MOSFET of claim 1, wherein said second insulation layer is SRO (Silicon Rich Oxide).

5. The trench MOSFET of claim 1, wherein said barrier layer is Ti/TiN or Co/TiN or Ta/TiN;

6. The trench MOSFET of claim 1, wherein said source-body contact trenches are filled with W metal or Al alloys or Cu.

7. The trench MOSFET of claim 1, wherein said front source metal is Al alloys or Cu overlying barrier layer of Ti/TiN or Co/TiN or Ta/TiN which covers the surface of said second insulation layer and fills said source-body contact trench when said source-body contact trench is filled with same material as front source metal.

8. The trench MOSFET of claim 1, wherein said front source metal is Al alloys or Cu overlying a layer of Ti or Ti/TiN which covering the front surface of said second insulation layer and said W metal plug when said source-body contact trench is filled with W metal.

9. The trench MOSFET of claim 1, wherein said drain metal is Ti/Ni/Ag.

11. The method of claim 9, wherein said pad oxide is about 100˜

500 angstrom.

12. The method of claim 9, wherein said Silicon Nitride is about 1000˜

2000 angstrom.

13. The method of claim 9, wherein said thick oxide is about 4000˜

8000 angstrom.

10. A method for manufacturing a trench MOSFET with terrace gate and improved source-body contact comprising the steps of:

growing epitaxial layer on a heavily doped substrate;

forming a thin pad layer followed with deposition of a silicon nitride and a thick oxide layer;

applying a trench mask to open a plurality of gate trenches into the epitaxial layer;

following with down-stream plasma silicon etch;

growing and removing a sacrificial oxide;

forming a gate oxide and depositing a doped polysilicon layer;

removing the doped polysilicon layer from surface of thick oxide layer and leave the doped polysilicon in gate trenches;

removing the thick oxide layer and silicon nitride layer;

forming body regions by ion implantation into the epitaxial layer followed by diffusion;

forming source regions by ion implantation near the top surface of body regions followed by diffusion;

depositing an oxide interlayer to define a concave area;

applying a contact mask with contact opening larger than the concave area and etching said terrace oxide interlayer with CD defined by contact mask to a certain depth;

opening the source-body contact hole by dry oxide etching and dry silicon etching into P body region with CD defined by said concave area;

implanting BF2 ion through said source-body contact trench with the same type dopant as the body region around the sidewalls and bottoms of said source-body contact trench within P body region followed by a step of RTA to activate BF2 ion;

depositing barrier layer of Ti/TiN or Co/TiN or Ta/TiN lining inner surface of source-body contact or lining inner surface of source-body contact and onto front surface of terrace oxide interlayer;

depositing W metal refilling into source-body contact and remove it from top surface of the oxide interlayer, then followed by deposition of Ti or Ti/N and Al alloys or Cu successively or depositing Al alloys or Cu refilling into source-body contact covering barrier layer as source-body contact plug and source metal as well;

depositing a layer of Ti/Ni/Ag on the rear side of wafer as drain metal.