FIELD EFFECT DEVICE INCLUDNG RECESSED AND ALIGNED GERMANIUM CONTAINING CHANNEL

• US 20100200934A1
• Filed: 02/09/2010
• Published: 08/12/2010
• Est. Priority Date: 02/12/2009
• Status: Active Grant

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Yang, Haining S., Greene, Brian J., Chen, Xiangdong
• Granted Patent: US 8,217,470 B2
• Time in Patent Office: Days
• US Class Current: 257/402
• CPC Class Codes: H01L 21/28194 by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition H01L21/28202 takes precedence
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/495 the conductor material next to the insulator being a simple metal, e.g. W, Mo H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/66651 with a single crystalline channel formed on the silicon substrate after insulating device isolation
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain

Abstract

A field effect structure and a method for fabricating the field effect structure include a germanium containing channel interposed between a plurality of source and drain regions. The germanium containing channel is coplanar with the plurality of source and drain regions, and the germanium containing channel includes a germanium containing material having a germanium content greater than the germanium content of the plurality of source and drain regions.

Claims

1. A semiconductor structure comprising:

a semiconductor substrate;

a gate aligned over a channel within the semiconductor substrate; and

a plurality of source/drain regions separated by the channel, wherein;

the channel is coplanar with the plurality of source/drain regions;

the channel comprises a germanium containing material having a germanium content greater than a germanium content of the plurality of source/drain regions.

2. The semiconductor structure of claim 1 wherein the semiconductor substrate comprises a bulk semiconductor substrate.

3. The semiconductor substrate of claim 1 wherein the semiconductor substrate comprises a semiconductor-on-insulator substrate.

4. The semiconductor structure of claim 1 wherein the semiconductor substrate comprises a hybrid orientation substrate.

5. The semiconductor structure of claim 1 wherein the germanium containing material comprises germanium.

6. The semiconductor structure of claim 1 wherein the germanium containing material comprises a silicon-germanium alloy.

7. The semiconductor structure of claim 1 wherein the channel has a wider linewidth than the gate.

8. The semiconductor structure of claim 1 further comprising a U shaped gate dielectric interposed between the gate and the semiconductor substrate.

9. The semiconductor structure of claim 1 wherein the U shaped gate dielectric comprises a high dielectric constant dielectric material.

10. A method for fabricating a semiconductor structure comprising:

forming a gate aligned over a channel within a semiconductor substrate;

forming a spacer adjoining the gate;

stripping the gate to leave remaining the spacer that exposes the semiconductor substrate;

etching the semiconductor substrate to form a recess within the semiconductor substrate aligned with the spacer;

forming a germanium containing channel layer within the recess; and

forming a plurality of source/drain regions within the semiconductor substrate and separated by the channel, wherein;

the channel is coplanar with the plurality of source/drain regions;

the germanium containing channel layer comprises a germanium containing material having a germanium content greater than a germanium content of the plurality of source/drain regions.

11. The method of claim 10 wherein the semiconductor substrate comprises a bulk semiconductor substrate.

12. The method of claim 10 wherein the semiconductor substrate comprises a semiconductor-on-insulator substrate.

13. The method of claim 10 wherein the semiconductor substrate comprises a hybrid orientation substrate.

14. The method of claim 10 wherein the germanium containing material comprises germanium.

15. The method of claim 10 wherein the germanium containing material comprises a silicon-germanium alloy.

16. The method of claim 10 wherein the channel has a wider linewidth than the gate.

17. The method of claim 10 further comprising forming a gate dielectric interposed the gate and the semiconductor substrate.

18. The method of claim 17 wherein the gate dielectric has a U shape.

19. The method of claim 18 wherein the gate dielectric comprises a high dielectric constant dielectric material.