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SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME

  • US 20100200969A1
  • Filed: 01/13/2010
  • Published: 08/12/2010
  • Est. Priority Date: 02/09/2009
  • Status: Active Grant
First Claim
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1. A semiconductor package, comprising:

  • a chip having a first surface and a second surface opposite to the first surface, wherein the chip comprises a first pad located on the first surface;

    a carrier having a third surface and a fourth surface opposite to the third surface, wherein the carrier comprises a second pads located on the third surface, and the chip is disposed on the carrier;

    at least one bonding wire electrically connecting the chip to the carrier and comprising;

    a first end bonded to the first pad so as to form a first bond portion; and

    a second end bonded to the second pad so as to form a second bond portion, wherein the second bond portion comprises a fishtail region which comprises at least one scrubbing protrusion being integrally formed thereon; and

    a molding compound sealing the chip and the bonding wire and covering the carrier.

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