Dopant Enhanced Interconnect

• US 20100200991A1
• Filed: 02/12/2010
• Published: 08/12/2010
• Est. Priority Date: 03/15/2007
• Status: Abandoned Application

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Indukuri, Tejaswi K., Clarke, James S., Akolkar, Rohan, Balakrishnan, Sridhar, Lavoie, Adrien R.
• Application Number:
  US12/705,143
• Publication Number:
  US 20100200991A1
• Time in Patent Office: Days
• US Class Current: 257/751
• CPC Class Codes: C23C 16/045 Coating cavities or hollow spaces, e.g. interior of tubes; Infiltration of porous substrates
• CPC Class Codes: C23C 16/18 from metallo-organic compounds
• CPC Class Codes: C23C 16/45529 specially adapted for making a layer stack of alternating different compositions or gradient compositions
• CPC Class Codes: C23C 16/45542 Plasma being used non-continuously during the ALD reactions
• CPC Class Codes: H01L 21/2855 by physical means, e.g. sputtering, evaporation H01L21/28518 - H01L21/28537 and H01L21/28568 take precedence
• CPC Class Codes: H01L 21/28562 Selective deposition
• CPC Class Codes: H01L 21/76843 formed in openings in a dielectric
• CPC Class Codes: H01L 21/76873 for electroplating
• CPC Class Codes: H01L 21/76886 Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances

Abstract

Techniques are disclosed that enable an interconnect structure that is resistance to electromigration. A liner is deployed underneath a seed layer of the structure. The liner can be a thin continuous and conformal layer, and may also limit oxidation of an underlying barrier (or other underlying surface). A dopant that is compatible (non-alloying, non-reactive) with the liner is provided to alloy the seed layer, and allows for dopant segregation at the interface at the top of the seed layer. Thus, electromigration performance is improved.

Claims

1. An interconnect device, comprising:

a liner deposited over a trench and/or via structure formed in a dielectric material; and

an interconnect, formed on the liner, the interconnect comprising a dopant that does not alloy or react with the liner, wherein the dopant is present at a top surface of the interconnect.

2. The device of claim 1, further comprising:

a protective layer deposited on the interconnect along the top surface.

3. The device of claim 1, further comprising:

a barrier layer deposited on the trench and/or via such that the liner is deposited on the barrier layer, the barrier layer being implemented with tantalum, tantalum nitride, titanium, titanium nitride, or combinations thereof.

4. The device of claim 1 wherein the liner is implemented with ruthenium, cobalt, or nickel.

5. The device of claim 1 wherein the interconnect is fabricated by applying heat to an alloyed seed layer upon which a layer of interconnect fill metal is deposited.

6. The device of claim 1 wherein the interconnect is copper alloyed with magnesium and/or manganese.

7. An interconnect device, comprising:

a barrier layer deposited on a trench and/or via structure formed in a dielectric material, the barrier layer being implemented with tantalum, tantalum nitride, titanium, titanium nitride, or combinations thereof;

a liner deposited on the barrier layer, wherein the liner is implemented with ruthenium, cobalt, or nickel; and

an interconnect, formed on the liner, the interconnect comprising a dopant that does not alloy or react with the liner, wherein the dopant is present at a top surface of the interconnect.

8. The device of claim 7 wherein the interconnect is copper alloyed with magnesium and/or manganese.

9. A method for forming an interconnect device, the method comprising:

depositing a liner over a trench and/or via structure provided in a dielectric material;

forming, on the liner, an alloyed seed layer comprising a dopant that does not alloy or react with the liner;

depositing a layer of interconnect fill metal on the alloyed seed layer;

depositing a protective layer on a top surface of the interconnect fill metal; and

diffusing the dopant away from the liner toward the top surface of the interconnect fill metal.

10. The method of claim 9 wherein prior to depositing a liner, the method comprises:

forming the trench and/or via in the dielectric layer.

11. The method of claim 9 wherein prior to depositing a liner, the method further comprises:

depositing a barrier layer on the trench and/or via such that the liner is subsequently deposited on the barrier layer, wherein the barrier layer being implemented with tantalum, tantalum nitride, titanium, titanium nitride, or combinations thereof and the liner is implemented with ruthenium, cobalt, or nickel.

12. The method of claim 9 wherein prior to depositing a protective layer on a top surface of the interconnect fill metal, the method comprises:

planarizing the device to a desired level.

13. The method of claim 9 wherein the layer of interconnect fill metal is applied by a plating process.

14. The method of claim 9 wherein forming an alloyed seed layer comprising a dopant that does not alloy or react with the liner comprises depositing a pre-alloyed seed metal.

15. The method of claim 14 wherein the pre-alloyed seed metal is copper alloyed with magnesium and/or manganese.

16. The method of claim 9 wherein forming an alloyed seed layer comprising a dopant that does not alloy or react with the liner comprises depositing alternating layers of seed metal and alloy metal, and then annealing to combine the layers into a homogenous or graded alloyed seed layer.

17. The method of claim 16 wherein the seed metal is copper and the alloy metal is magnesium and/or manganese.

18. The method of claim 9 wherein diffusing the dopant away from the liner is a dedicated dopant segregation process.

19. The method of claim 9 wherein diffusing the dopant away from the liner is carried out by exploiting thermal budget of a process included in forming the interconnect device.

20. The method of claim 19 wherein depositing a protective layer on a top surface of the interconnect fill metal provides the thermal budget.