REDUCTION OF DEAD-TIME DISTORTION IN CLASS D AMPLIFIERS

• US 20100201443A1
• Filed: 02/11/2009
• Published: 08/12/2010
• Est. Priority Date: 02/11/2009
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Kaya, Cetin, Shook, Adam
• Granted Patent: US 7,795,970 B2
• Time in Patent Office: Days
• US Class Current: 330/251
• CPC Class Codes: H03F 3/217 Class D power amplifiers; Switching amplifiers

Abstract

Pulse-width-modulating class D amplifier with an H-bridge output stage, and method of operating the same. in which output stage dead-time is compensated. Offset logic circuitry detects various dead-time-related conditions at push-pull output drivers, and generates an offset signal applied to the amplified differential input signal, to adjust the time at which the voltage at differential signal lines crosses a ramp reference waveform. The offset signal can correspond to the duration of a disturbance (dead-time at one driver in combination with an active signal at the active driver), or the sum of that disturbance duration with a dead-time at the active driver. The offset signal is generated by charging a capacitor for the duration of this disturbance, or disturbance plus dead-time. According to another approach, error is reduced by charging a capacitor for each transition of the signal for a duration of the dead-time of the active driver. Total harmonic distortion is reduced without requiring increased circuit complexity and without shortening the dead-time to unsafe margins.

Claims

1. A class D output amplifier circuit, comprising:

a first push-pull output stage, comprising a first pull-up transistor and a first pull-down transistor having conduction paths connected in series between first and second reference voltages and defining a first output node at a connection between the conduction paths, each of the first pull-up and pull-down transistors having control terminals;

a second push-pull output stage, comprising a second pull-up transistor and a second pull-down transistor having conduction paths connected in series between the first and second reference voltages and defining a second output node at the a connection between the conduction paths, each of the second pull-up and pull-down transistors having control terminals;

a first drive circuit, having outputs coupled to the control terminals of the first pull-up and pull-down transistors, and having an input, the first drive circuit for controlling driving its outputs in response to a logic signal at its input in such a manner that, responsive to a transition at its input, the first drive circuit issues signals at its outputs so that both of the first pull-up and pull-down transistors are off for a selected dead-time;

a second drive circuit, having outputs coupled to the control terminals of the second pull-up and pull-down transistors, and having an input, the second drive circuit for controlling driving its outputs in response to a logic signal at its input in such a manner that, responsive to a transition at its input, the second drive circuit issues signals at its outputs so that both of the second pull-up and pull-down transistors are off for a selected dead-time;

a first comparator having a first input for receiving a first differential signal line, having a second input for receiving a reference waveform, having a third input for receiving an offset differential voltage, and having an output coupled to the input of the first drive circuit;

a second comparator having a first input for receiving a second differential signal line, having a second input for receiving the reference waveform, having a third input for receiving an offset signal, and having an output coupled to the input of the second drive circuit; and

offset logic circuitry, having inputs coupled to the first and second drive circuits, and having an outputs for driving an offset signal to the third input of one of the first and second comparators, the offset signal corresponding to a measured time duration in the operation of a corresponding one of the first or second drive circuits.

2. The circuit of claim 1, wherein the offset logic circuitry comprises:

a first logic circuit for sensing the dead-time at the output of the second drive circuit in combination with a first selected logic level being driven from the first drive circuit;

a first capacitor circuit, coupled to the output of the first logic circuit, for charging to a voltage corresponding to the time sensed by the first logic circuit;

a second logic circuit for sensing the dead-time at the output of the first drive circuit in combination with a first selected logic level being driven from the second logic circuit; and

a second capacitor circuit, coupled to the output of the second logic circuit, for charging to a voltage corresponding to the time sensed by the second logic circuit;

wherein the offset signal corresponds to voltage stored at one or both of the first and second capacitor circuits.

3. The circuit of claim 2, wherein the reference waveform corresponds to a periodic time-varying voltage at a pulse-width-modulation frequency;

wherein the offset logic circuitry further comprises;

gating circuitry, for enabling the first and second logic circuits during a first half-cycle of the reference waveform and for blocking operation of the first and second logic circuits during a second half-cycle of the reference waveform.

4. The circuit of claim 1, wherein the offset logic circuitry comprises:

a first dead-time logic function for sensing the dead-time at the output of the first drive circuit;

a second dead-time logic function for sensing the dead-time at the output of the second drive circuit;

circuitry for charging the first capacitor circuit to a voltage corresponding to a sum of the sensed dead-time at the first drive circuit plus the dead-time at the output of the second drive circuit in combination with the first selected logic level being driven from the first drive circuit, responsive to a positive polarity differential signal at the first and second differential signal lines; and

circuitry for charging the second capacitor circuit to a voltage corresponding to a sum of the sensed dead-time at the second drive circuit plus the dead-time at the output of the first drive circuit in combination with the first selected logic level being driven from the second drive circuit, responsive to a negative polarity differential signal at the first and second differential signal lines.

5. The circuit of claim 1, wherein each of the first and second comparators comprises:

a first differential stage receiving a differential signal corresponding to the input differential signal, and having first and second outputs;

a second differential stage, having inputs coupled to the third input to receive the offset signal in the form of a differential signal, and having first and second outputs coupled to the first and second outputs of the first differential stage;

and a differential output stage for generating an output signal corresponding to the outputs of the first and second differential stages.

6. The circuit of claim 1, wherein the offset logic circuitry comprises:

a first offset logic function, having inputs coupled to the first and second drive circuits, and having an output coupled to the third input of the first comparator, comprising;

a first low-to-high transition function, for sensing a time duration between initiation of the dead-time at the output of the first drive circuit and a time at which the first output node is driven high, during a first half-cycle of the reference waveform;

a first low-to-high capacitor function, for charging to a voltage corresponding to the time duration sensed by the first low-to-high transition function;

a first high-to-low transition function, for sensing a time duration between initiation of the dead-time at the output of the first drive circuit and a time at which the first output node is driven low, during a second half-cycle of the reference waveform; and

a first high-to-low capacitor function, for charging to a voltage corresponding to the time duration sensed by the first high-to-low transition function; and

a second offset logic function, having inputs coupled to the first and second drive circuits, and having an output coupled to the third input of the second comparator, comprising;

a second low-to-high transition function, for sensing a time duration between initiation of the dead-time at the output of the second drive circuit and a time at which the second output node is driven high, during a first half-cycle of the reference waveform;

a second low-to-high capacitor function, for charging to a voltage corresponding to the dead-time sensed by the second low-to-high transition function;

a second high-to-low transition function, for sensing a time duration between initiation of the dead-time at the output of the second drive circuit and a time at which the second output node is driven low, during a second half-cycle of the reference waveform; and

a second high-to-low capacitor function, for charging to a voltage corresponding to the dead-time sensed by the second high-to-low transition function.

7. The circuit of claim 6, wherein the voltage stored by the first and second low-to-high capacitor functions is applied to the first and second comparators, respectively, during the second half-cycle, and wherein the voltage stored by the first and second high-to-low capacitor functions is applied to the first and second comparators, respectively, during the first half-cycle.

8. The circuit of claim 1, further comprising:

an integrating differential amplifier, receiving an input differential signal and for generating an amplified differential signal at the first and second differential signal lines in response to the input differential signal.

9. The circuit of claim 8, wherein the integrating differential amplifier comprises:

a differential amplifier stage; and

a first order feedback network.

10. A method of operating a class D output drive circuit, comprising:

receiving an input differential signal;

generating a differential signal corresponding to the input differential signal at first and second differential signal lines;

comparing the voltage at the first differential signal line with a reference waveform to produce a first comparator output signal;

comparing the voltage at the second differential signal line with the reference waveform to produce a second comparator output signal;

controlling a first push-pull output stage to drive a first output node, coupled to one side of a load, responsive to the first comparator output signal, the controlling comprising enforcing a high impedance state at the first output node for a selected dead-time responsive to transitions of the first comparator output signal;

controlling a second push-pull output stage to drive a second output node, coupled to another side of the load, responsive to the second comparator output signal, comprising enforcing a high impedance state at the second output node for a selected dead-time responsive to transitions of the second comparator output signal;

wherein a differential voltage appears between the first and second output nodes for a duration corresponding to the input differential signal;

and further comprising;

adjusting the duration of the differential voltage between the first and second output nodes responsive to a duration of a high-impedance condition at one of the first and second output nodes.

11. The method of claim 10, wherein the adjusting step comprises:

charging a first capacitor for a time corresponding to a duration of a high-impedance state applied by the second push-pull output stage in combination with the first push-pull output stage driving the first output node to a first state; and

then applying voltage from the first capacitor as an offset to the first differential signal line for the comparing step.

12. The method of claim 11, wherein the steps of charging the first capacitor and applying voltage from the first capacitor are performed responsive to an input differential signal of a first polarity;

and further comprising, responsive to an input differential signal of a second polarity;

charging a second capacitor for a time corresponding to a duration of a high-impedance state applied by the first push-pull output stage in combination with the second push-pull output stage driving the second output node to the first state; and

then applying voltage from the second capacitor as an offset to the second differential signal line for the comparing step.

13. The method of claim 11, wherein the step of charging the first capacitor comprises:

charging the first capacitor for a time corresponding to the sum of a duration of a high-impedance state applied by the second push-pull output stage in combination with the first push-pull output stage driving the first output node to the first state, plus a duration of a high-impedance state applied by the first push-pull output stage;

and wherein the step of charging the second capacitor comprises;

charging the second capacitor for a time corresponding to the sum of a duration of a high-impedance state applied by the first push-pull output stage in combination with the second push-pull output stage driving the second output node to the first state, plus a duration of a high-impedance state applied by the second push-pull output stage.

14. The method of claim 10, wherein the reference waveform corresponds to a periodic time-varying voltage at a pulse-width-modulation frequency:

wherein the adjusting step comprises;

during a first half-cycle of the reference waveform, charging a first low-to-high capacitor for a duration beginning with a high-impedance state applied by the first push-pull output stage and ending with the first output node making a transition to a high level;

during the first half-cycle of the reference waveform, charging a second low-to-high capacitor for a duration beginning with a high-impedance state applied by the second push-pull output stage and ending with the second output node making a transition to the high level;

during a second half-cycle of the reference waveform, charging a first high-to-low capacitor for a duration beginning with a high-impedance state applied by the first push-pull output stage and ending with the first output node making a transition to a low level;

during the second half-cycle of the reference waveform, charging a second high-to-low capacitor for a duration beginning with a high-impedance state applied by the second push-pull output stage and ending with the second output node making a transition to the low level;

during the second half-cycle of the reference waveform, applying voltage from the first low-to-high capacitor to the first differential signal line and applying voltage from the second low-to-high capacitor to the second differential signal line; and

during a next first half-cycle of the reference waveform, applying voltage from the first high-to-low capacitor to the first differential signal line and applying voltage from the second high-to-low capacitor as an offset to the second differential signal line for the comparing step.