DIGITAL POTENTIOMETER ARCHITECTURE WITH MULTIPLE STRING ARRAYS ALLOWING FOR INDEPENDENT CALIBRATION IN RHEOSTAT MODE

• US 20100201476A1
• Filed: 02/06/2009
• Published: 08/12/2010
• Est. Priority Date: 02/06/2009
• Status: Active Grant

• Current Assignee: Analog Devices, Inc.
• Original Assignee: Analog Devices, Inc.
• Inventors: TALEGAONKAR, Mrinmay, RAMALINGAM, Kirubakaran, JHA, Kaushal Kumar, VYAS, Bhargav
• Granted Patent: US 7,982,581 B2
• Time in Patent Office: Days
• US Class Current: 338/118
• CPC Class Codes: H03H 7/24 Frequency- independent attenuators

Abstract

Digital potentiometer architecture is disclosed, composing of an integrated circuit containing multiple string arrays, each having a plurality of switching devices and an array of resistors. The insertion of an additional string array between the input terminals and the wiper, allows for the disconnection of a common string array and for the independent calibration of the resistance between each input terminal and the wiper.

Claims

1. An integrated circuit, comprising:

first and second input terminals;

a wiper terminal;

a first array of resistors connected in series, the first array of resistors having an output;

a plurality of first switching devices connecting the first input terminal to selected tap points of the first array of resistors;

a second array of resistors connected in series, the second array of resistors having an output;

a plurality of second switching devices connecting the second input terminal to selected tap points of the second array of resistors;

a third array of resistors connected in series, the third array being connected in series with the first array of resistors, the third array of resistors having an input and output;

a plurality of third switching devices connecting selected tap points of the third array of resistors to the wiper terminal;

a fourth array of resistors connected in series, the fourth array being connected in series with the second array of resistors, the fourth array of resistors having an input and output;

a plurality of fourth switching devices connecting selected tap points of the fourth array of resistors to the wiper terminal;

wherein the third array of resistors is connected to the fourth array of resistors only at the outputs of the third and fourth arrays of resistors, the outputs of the third and fourth arrays of resistors being connected to the wiper terminal.

2. The integrated circuit according to claim 1, wherein a fifth array of resistors is connected in series with the first array of resistors and the third array of resistors, the fifth array of resistors having an input and output.

3. The integrated circuit according to claim 1, wherein a sixth array of resistors is connected in series with the second array of resistors and the fourth array of resistors, the sixth array of resistors having an input and output.

4. The integrated circuit according to claim 2, wherein the input of the fifth array of resistors connects to the output of the first array of resistors, the output of the fifth array of resistors connects to the input of the third array of resistors.

5. The integrated circuit according to claim 3, wherein the input of the sixth array of resistors connects to the output of the second array of resistors, the output of the sixth array of resistors connects to the input of the fourth array of resistors.

6. The integrated circuit according to claim 2, wherein a plurality of fifth switching devices connects the output of the first array of resistors to selected tap points of the fifth array of resistors.

7. The integrated circuit according to claim 3, wherein a plurality of sixth switching devices connects the output of the second array of resistors to selected tap points of the sixth array of resistors.

8. The integrated circuit from claim 1, wherein the switching devices are complementary metal-oxide semiconductor (CMOS) devices.

9. An integrated circuit, comprising:

first and second input terminals;

first and second wiper terminals;

a first array of resistors connected in series, the first array of resistors having an output;

a plurality of first switching devices connecting the first input terminal to selected tap points of the first array of resistors;

a second array of resistors connected in series, the second array of resistors having an output;

a plurality of second switching devices connecting the second input terminal to selected tap points of the second array of resistors;

a third array of resistors connected in series, the third array being connected in series with the first array of resistors, the third array of resistors having an input and output;

a plurality of third switching devices connecting selected tap points of the third array of resistors to the first wiper terminal;

a fourth array of resistors connected in series, the fourth array being connected in series with the second array of resistors, the fourth array of resistors having an input and output;

a plurality of fourth switching devices connecting selected tap points of the fourth array of resistors to the second wiper terminal;

wherein the third array of resistors is disconnected from the fourth arrays of resistors.

10. The integrated circuit according to claim 9, wherein a fifth array of resistors is connected in series with the first array of resistors and the third array of resistors, the fifth array of resistors having an input and output.

11. The integrated circuit according to claim 9, wherein a sixth array of resistors is connected in series with the second array of resistors and the fourth array of resistors, the sixth array of resistors having an input and output.

12. The integrated circuit according to claim 10, wherein the input of the fifth array of resistors connects to the output of the first array of resistors, the output of the fifth array of resistors connects to the input of the third array of resistors.

13. The integrated circuit according to claim 11, wherein the input of the sixth array of resistors connects to the output of the second array of resistors, the output of the sixth array of resistors connects to the input of the fourth array of resistors.

14. The integrated circuit according to claim 10, wherein a plurality of fifth switching devices connects the output of the first array of resistors to selected tap points of the fifth array of resistors.

15. The integrated circuit according to claim 11, wherein a plurality of sixth switching devices connects the output of the second array of resistors to selected tap points of the sixth array of resistors.

16. The integrated circuit from claim 9, wherein the switching devices are complementary metal-oxide semiconductor (CMOS) devices.

17. The integrated circuit from claim 10, wherein at least one additional array of resistors is connected in series with the fifth array of resistors and the third array of resistors.

18. The integrated circuit from claim 11, wherein at least one additional array of resistors is connected in series with the sixth array of resistors and the fourth array of resistors.

19. The integrated circuit from claim 17, wherein at least one additional plurality of switching devices connects to the at least one additional array of resistors at selected tap points.

20. The integrated circuit from claim 18, wherein at least one additional plurality of switching devices connects to the at least one additional array of resistors at selected tap points.