DIGITAL POTENTIOMETER ARCHITECTURE WITH MULTIPLE STRING ARRAYS ALLOWING FOR INDEPENDENT CALIBRATION IN RHEOSTAT MODE
First Claim
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1. An integrated circuit, comprising:
- first and second input terminals;
a wiper terminal;
a first array of resistors connected in series, the first array of resistors having an output;
a plurality of first switching devices connecting the first input terminal to selected tap points of the first array of resistors;
a second array of resistors connected in series, the second array of resistors having an output;
a plurality of second switching devices connecting the second input terminal to selected tap points of the second array of resistors;
a third array of resistors connected in series, the third array being connected in series with the first array of resistors, the third array of resistors having an input and output;
a plurality of third switching devices connecting selected tap points of the third array of resistors to the wiper terminal;
a fourth array of resistors connected in series, the fourth array being connected in series with the second array of resistors, the fourth array of resistors having an input and output;
a plurality of fourth switching devices connecting selected tap points of the fourth array of resistors to the wiper terminal;
wherein the third array of resistors is connected to the fourth array of resistors only at the outputs of the third and fourth arrays of resistors, the outputs of the third and fourth arrays of resistors being connected to the wiper terminal.
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Abstract
Digital potentiometer architecture is disclosed, composing of an integrated circuit containing multiple string arrays, each having a plurality of switching devices and an array of resistors. The insertion of an additional string array between the input terminals and the wiper, allows for the disconnection of a common string array and for the independent calibration of the resistance between each input terminal and the wiper.
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Citations
20 Claims
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1. An integrated circuit, comprising:
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first and second input terminals; a wiper terminal; a first array of resistors connected in series, the first array of resistors having an output; a plurality of first switching devices connecting the first input terminal to selected tap points of the first array of resistors; a second array of resistors connected in series, the second array of resistors having an output; a plurality of second switching devices connecting the second input terminal to selected tap points of the second array of resistors; a third array of resistors connected in series, the third array being connected in series with the first array of resistors, the third array of resistors having an input and output; a plurality of third switching devices connecting selected tap points of the third array of resistors to the wiper terminal; a fourth array of resistors connected in series, the fourth array being connected in series with the second array of resistors, the fourth array of resistors having an input and output; a plurality of fourth switching devices connecting selected tap points of the fourth array of resistors to the wiper terminal; wherein the third array of resistors is connected to the fourth array of resistors only at the outputs of the third and fourth arrays of resistors, the outputs of the third and fourth arrays of resistors being connected to the wiper terminal. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. An integrated circuit, comprising:
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first and second input terminals; first and second wiper terminals; a first array of resistors connected in series, the first array of resistors having an output; a plurality of first switching devices connecting the first input terminal to selected tap points of the first array of resistors; a second array of resistors connected in series, the second array of resistors having an output; a plurality of second switching devices connecting the second input terminal to selected tap points of the second array of resistors; a third array of resistors connected in series, the third array being connected in series with the first array of resistors, the third array of resistors having an input and output; a plurality of third switching devices connecting selected tap points of the third array of resistors to the first wiper terminal; a fourth array of resistors connected in series, the fourth array being connected in series with the second array of resistors, the fourth array of resistors having an input and output; a plurality of fourth switching devices connecting selected tap points of the fourth array of resistors to the second wiper terminal; wherein the third array of resistors is disconnected from the fourth arrays of resistors. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20)
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Specification