HIGH RELIABILITY OTP MEMORY

• US 20100202183A1
• Filed: 02/05/2010
• Published: 08/12/2010
• Est. Priority Date: 02/06/2009
• Status: Active Grant

• Current Assignee: Synopsys Incorporated
• Original Assignee: Sidense Corporation (Synopsys Incorporated)
• Inventors: KURJANOWICZ, Wlodek
• Granted Patent: US 8,213,211 B2
• Time in Patent Office: Days
• US Class Current: 365/94
• CPC Class Codes: G11C 16/22 Safety or protection circuits preventing unauthorised or accidental access to memory cells
• CPC Class Codes: G11C 17/16 using electrically-fusible links
• CPC Class Codes: G11C 17/18 Auxiliary circuits, e.g. for writing into memory

Abstract

A method and system for improving reliability of OTP memories, and in particular anti-fuse memories, by storing one bit of data in at least two OTP memory cells. Therefore each bit of data is read out by accessing the at least two OTP memory cells at the same time in a multi-cell per bit mode. By storing one bit of data in at least two OTP memory cells, defective cells or weakly programmable cells are compensated for since the additional cell or cells provide inherent redundancy. Program reliability is ensured by programming the data one bit at a time, and verifying all programmed bits in a single-ended read mode, prior to normal operation where the data is read out in the multi-cell per bit mode. Programming and verification is achieved at high speed and with minimal power consumption using a novel program/verify algorithm for anti-fuse memory. In addition to improved reliability, read margin and read speed are improved over single cell per bit memories.

Claims

1. A method for programming one time programmable (OTP) memory cells comprising:

i) programming input data with first programming parameters;

ii) identifying bits of the input data which failed programming with the first programming parameters as failed bits;

iii) reprogramming the failed bits with second programming parameters different from the first programming parameters; and

,

iv) repeating the method at ii) if at least one bit is identified as failing the reprogramming.

2. The method of claim 1, wherein identifying includes inhibiting bits of the input data which passed programming from further programming.

3. The method of claim 1, wherein the first programming parameters include a first programming voltage level and a first duration of time, and programming includes driving a selected wordline with the first programming voltage level for the first duration of time.

4. The method of claim 3, wherein the second programming parameters include a second programming voltage level and a second duration of time, and reprogramming includes driving the selected wordline with the second programming voltage level for the second duration of time.

5. The method of claim 4, wherein the first programming voltage level and the second programming voltage level are the same.

6. The method of claim 4, wherein the first programming voltage level is less than the second programming voltage level.

7. The method of claim 4, wherein the first duration of time is less than the second duration of time.

8. The method of claim 1, wherein identifying includes read verifying programmed data programmed in i) by driving a selected wordline with a first read voltage.

9. The method of claim 8, wherein repeating includes read verifying the reprogrammed data reprogrammed in iii) by driving the selected wordline with a second read voltage.

10. The method of claim 9, wherein the first read voltage is less than the second read voltage.

11. The method of claim 10, wherein the second read voltage is the same or lower than a read voltage used during normal read operations.

12. The method of claim 9, wherein a read operation is executed after all bits of the input data have been successfully programmed by selecting at least four memory cells concurrently in a differential-redundant read mode to read one bit of data from every four OTP memory cells.

13. The method of claim 12, wherein selecting includes driving at least four wordlines concurrently with a third read voltage for accessing the at least four memory cells, the third read voltage being lower than the second read voltage.

14. The method of claim 12, wherein selecting includes driving at least four wordlines concurrently for accessing the at least four memory cells connected to different bitlines, and operating a sense amplifier to compare levels corresponding to combinations of the different bitlines to each other.

15. The method of claim 12, wherein selecting includes driving one wordline for accessing the at least four memory cells connected to different bitlines, and operating a sense amplifier to compare levels of the different bitlines to each other.

16. The method of claim 9, wherein repeating further includes comparing the reprogrammed data to the input data, the at least one bit being identified as failing the reprogramming if at least one bit of the reprogrammed data fails to correspond with at least one bit of the input data.

17. The method of claim 9, wherein a read operation is executed after all bits of the input data have been successfully programmed by selecting at least two memory cells concurrently in one of a redundant read mode and a differential read mode to read one bit of data from every two OTP memory cells.

18. The method of claim 17 wherein selecting includes driving at least two wordlines concurrently with a third read voltage for accessing the at least two memory cells, the third read voltage being lower than the second read voltage.

19. The method of claim 17, wherein selecting includes driving at least two wordlines concurrently for accessing the at least two memory cells connected to one bitline, and operating a sense amplifier to compare a bitline level corresponding to the one bitline to a reference level.

20. The method of claim 17, wherein selecting includes driving at least two wordlines concurrently for accessing the at least two memory cells connected to different bitlines, and operating a sense amplifier to compare bitline levels corresponding to the different bitlines to each other.

21. The method of claim 17, wherein selecting includes driving one wordline for accessing the at least two memory cells connected to different bitlines.

22. The method of claim 21, wherein selecting includes coupling the different bitlines to complementary inputs of a sense amplifier, and operating the sense amplifier to compare levels of the different bitlines to each other.

23. The method of claim 21, wherein selecting includes coupling the different bitlines to one input of a sense amplifier, and operating the sense amplifier to compare a level corresponding to a combination of the different bitlines to a reference level.

24. The method of claim 23, wherein the level and the reference level is a voltage.

25. The method of claim 23, wherein the level and the reference level is a current.

26. A one time programmable memory system, comprising:

a memory array having one time programmable (OTP) cells connected to bitlines and wordlines;

a select circuit configurable to couple a variable number of OTP cells to a sense amplifier at the same time in response to an address and a selected read mode of operation; and

,

a mode selector for selecting the read mode of operation to control the select circuit to access one OTP cell per bit of data in a single-ended mode during a program or verify operation, and to control the select circuit to concurrently access at least two OTP cells per bit of data for sensing during a read operation.

27. The one time programmable memory system of claim 26, further including control logic for configuring the mode selector to operate in the single-ended mode during the program operation, the control logic executing a programming operation.

28. The one time programmable memory system of claim 26, further including a voltage circuit for providing a programming voltage during initial programming of the OTP cells.

29. The one time programmable memory system of claim 28, wherein the voltage circuit provides a first read voltage during a first read verify operation and a second read voltage during a second read verify operation.

30. The one time programmable memory system of claim 26, wherein the select circuit includes configurable row circuits and the memory array includes

a first wordline connected to a first OTP cell,

a second wordline connected to a second OTP cell,

a third wordline connected to a third OTP cell,

a fourth wordline connected to a fourth OTP cell,

a first bitline connected to the first OTP cell and the third OTP cell,

a second bitline connected to the second OTP cell and the fourth OTP cell, and

a sense amplifier for sensing a difference between the first bitline level and the second bitline level.

31. The one time programmable memory system of claim 30, wherein the configurable row circuits concurrently drive one pair of wordlines including the first wordline and the third wordline or the second wordline and the fourth wordline in a redundant read mode.

32. The one time programmable memory system of claim 30, wherein the configurable row circuits concurrently drive one pair of wordlines including the first wordline and the second wordline or the third wordline and the fourth wordline in a differential read mode.

33. The one time programmable memory system of claim 30, wherein the configurable row circuits concurrently drive the first wordline, the second wordline, the third wordline and the fourth wordline in a differential-redundant read mode.

34. The one time programmable memory system of claim 26, wherein the select circuit includes configurable column circuits and the memory array includes

a first bitline connected to a first OTP cell,

a second bitline connected to a second OTP cell,

a third bitline connected to a third OTP cell,

a fourth bitline connected to a fourth OTP cell,

a first sense line selectively coupled to the first and second bitline,

a second sense line selectively coupled to the third and forth bitline, and

a sense amplifier for sensing a difference between the first sense line level and the second sense line level.

35. The one time programmable memory system of claim 34, wherein the configurable column circuits concurrently couple one pair of bitlines including the first bitline and the second bitline to the first sense line, or the third bitline and the fourth bitline to the second sense line in a redundant read mode.

36. The one time programmable memory system of claim 34, wherein the configurable column circuits concurrently couple one pair of bitlines including the first bitline and the third bitline to the first sense line and the second sense line respectively, or the second bitline and the fourth bitline to the second sense line respectively, in a differential read mode.

37. The one time programmable memory system of claim 34, wherein the configurable column circuits concurrently couple the first bitline and the second bitline to the first sense line, and the third bitline and the fourth bitline to the second sense line in a differential-redundant read mode.