nvSRAM HAVING VARIABLE MAGNETIC RESISTORS

• US 20100202191A1
• Filed: 02/12/2009
• Published: 08/12/2010
• Est. Priority Date: 02/12/2009
• Status: Active Grant

• Current Assignee: Seagate Technology LLC (Seagate Technology Holdings Plc)
• Original Assignee: Seagate Technology LLC (Seagate Technology Holdings Plc)
• Inventors: Lu, Yong, Liu, Hongyue, Ahn, Yongchul, Khoueir, Antoine
• Granted Patent: US 8,194,438 B2
• Time in Patent Office: Days
• US Class Current: 365/154
• CPC Class Codes: G11C 11/412 using field-effect transistors only
• CPC Class Codes: G11C 14/0081 and the nonvolatile element is a magnetic RAM [MRAM] element or ferromagnetic cell

Abstract

Non-volatile static random access memory (nvSRAM) that has a six transistor static random access memory (6T SRAM) cell electrically connected to a non-volatile random access memory (nvRAM) cell. The nvRAM cell has first and second variable magnetic resistors and first, second and third transistors.

Claims

1. A non-volatile static random access memory (nvSRAM) comprising:

a six transistor static random access memory (6T SRAM) cell; and

a non-volatile random access memory (nvRAM) cell comprising a first variable magnetic resistor, a second variable magnetic resistor, a first transistor, a second transistor and a third transistor, the 6T SRAM cell electrically connected to the nvRAM cell.

2. The nvSRAM of claim 1 wherein the nvRAM cell comprises a first stack and a second stack in parallel, the first stack comprising the first variable magnetic resistor and the first transistor, the second stack comprising the second variable magnetic resistor and the second transistor, the first stack and the second stack each in series with the third transistor.

3. The nvSRAM of claim 2 wherein the first stack and the second stack are each electrically connected between the SRAM cell and the third transistor.

4. The nvSRAM of claim 2 wherein the first and second transistors are electrically connected to a first voltage source to enable the transistors, the third transistor is connected to a second voltage source to enable the third transistor, and the third transistor has a source/drain terminal that is electrically connected to a third voltage source.

5. The nvSRAM of claim 2 wherein the first and second stacks are arranged with the first and second variable magnetic resistors electrically between the first and second transistors, respectively, and the third transistor.

6. The nvSRAM of claim 1 wherein each of the variable magnetic resistors is a magnetic tunnel junction comprising a free layer, a pinned layer, and a tunneling layer therebetween.

7. A non-volatile static random access memory (nvSRAM) comprising:

a six transistor static random access memory (6T SRAM) cell; and

a non-volatile random access memory (nvRAM) cell comprising a first stack and a second stack connected in parallel to the 6T SRAM cell, and a transistor connected in series to each of the first stack and the second stack, the stacks positioned electrically between the 6T SRAM cell and the transistor.

8. The nvSRAM of claim 7 wherein the first stack comprises a first variable magnetic resistor and a first transistor and the second stack comprises a second variable magnetic resistor and a second transistor, wherein the transistor connected in series to each of the first stack and the second stack is a third transistor.

9. The nvSRAM of claim 8 wherein each of the variable magnetic resistors is a magnetic tunnel junction comprising a free layer, a pinned layer, and a tunneling layer therebetween.

10. The nvSRAM of claim 8 wherein:

the first transistor and the second transistor are electrically connected to a first voltage source to enable the transistors,

the third transistor is connected to a second voltage source to enable the third transistor, and

the third transistor has a source/drain terminal that is electrically connected to a third voltage source.

11. The nvSRAM of claim 8 wherein the first and second stacks are arranged with the first and second variable magnetic resistors electrically between the first and second transistors, respectively, and the third transistor.

12. A method of storing data in a non-volatile static random access memory (nvSRAM), the method comprising:

entering a first bit of data in a six transistor static random access memory (6T SRAM) cell at a first node and entering a second bit of data in the 6T SRAM cell at a second node;

storing the first bit of data and the second bit of data by;

providing a first voltage to enable a first transistor electrically connected to the first node and to enable a second transistor electrically connected to the second node, the first transistor electrically connected to a first variable magnetic resistor with the first transistor electrically positioned between the first node and the first variable magnetic resistor, and the second transistor electrically connected to a second variable magnetic resistor with the second transistor electrically positioned between the second node and the second variable magnetic resistor; and

recalling the first bit of data and the second bit of data by;

grounding the 6T SRAM cell;

providing the first voltage; and

providing a second voltage to enable a third transistor electrically connected to the first variable magnetic resistor and to the second variable magnetic resistor, and

providing a third voltage to the third transistor.

13. The method of claim 12 wherein the step of storing the first bit of data and the second bit of data comprises providing a first voltage to enable a first stack electrically connected to the first node and to enable a second stack electrically connected to the second node, the first stack comprising the first transistor and the first variable magnetic resistor and the second stack comprising the second transistor and the second variable magnetic resistor.

14. The method of claim 12 wherein the step of storing the first bit of data and the second bit of data comprises providing a first voltage to enable a first stack electrically connected to the first node and to enable a second stack electrically connected to the second node, the first stack comprising the first transistor and a first magnetic tunnel junction and the second stack comprising the second transistor and a second magnetic tunnel junction.