ALL-BIT-LINE ERASE VERIFY AND SOFT PROGRAM VERIFY
First Claim
1. A method for erasing non-volatile storage, the method comprising:
- applying one or more erase pulses to a group of non-volatile storage elements, the group of non-volatile storage elements are associated with a plurality of bit lines, the group of non-volatile storage elements are associated with a plurality of word lines;
applying one or more non-negative compare voltages to at least a portion of the plurality of word lines after applying the one or more erase pulses;
allowing strong conduction currents of the plurality of bit lines to contribute to source line bias;
sensing conditions of the bit lines, the sensing is performed while applying the one or more compare voltages and allowing the strong conduction currents to contribute to source line bias;
determining whether the group of non-volatile storage elements are sufficiently erased to a negative threshold voltage based on the conditions; and
applying at least one additional erase pulse to the group of non-volatile storage elements if the group of non-volatile storage elements are not sufficiently erased.
3 Assignments
0 Petitions
Accused Products
Abstract
Techniques are disclosed herein for verifying that memory cells comply with a target threshold voltage that is negative. The technique can be used for an erase verify or a soft program verify. One or more erase pulses are applied to a group of non-volatile storage elements that are associated with bit lines and word lines. One or more non-negative compare voltages (e.g., zero volts) are applied to at least a portion of the word lines after applying the erase pulses. Conditions on the bit lines are sensed while holding differences between voltages on the bit lines substantially constant and while applying the one or more compare voltages. A determination is made whether the group is sufficiently erased based on the conditions. At least one additional erase pulse is applied to the group of non-volatile storage elements if the group of non-volatile storage elements are not sufficiently erased.
14 Citations
25 Claims
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1. A method for erasing non-volatile storage, the method comprising:
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applying one or more erase pulses to a group of non-volatile storage elements, the group of non-volatile storage elements are associated with a plurality of bit lines, the group of non-volatile storage elements are associated with a plurality of word lines; applying one or more non-negative compare voltages to at least a portion of the plurality of word lines after applying the one or more erase pulses; allowing strong conduction currents of the plurality of bit lines to contribute to source line bias; sensing conditions of the bit lines, the sensing is performed while applying the one or more compare voltages and allowing the strong conduction currents to contribute to source line bias; determining whether the group of non-volatile storage elements are sufficiently erased to a negative threshold voltage based on the conditions; and applying at least one additional erase pulse to the group of non-volatile storage elements if the group of non-volatile storage elements are not sufficiently erased. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A non-volatile storage device comprising:
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a group of non-volatile storage elements; a plurality of bit lines, the group of non-volatile storage elements are associated with the plurality of bit lines; a plurality of word lines associated with the group of non-volatile storage elements; and one or more managing circuits in communication with the group of non-volatile storage elements, the plurality of word lines, and the plurality of bit lines, the one or more managing circuits apply one or more erase pulses to the group of non-volatile storage elements, the one or more managing circuits apply one or more non-negative compare voltages to at least a portion of the plurality of word lines after applying the one or more erase pulses, the one or more managing circuits allow strong conduction currents of the plurality of bit lines to contribute to source line bias, the one or more managing circuits sense conditions on the bit lines while applying the one or more compare voltages and while allowing the strong conduction currents to contribute to source line bias, the one or more managing circuits determine whether the group of non-volatile storage elements are sufficiently erased to a negative threshold voltage based on the conditions, the one or more managing circuits apply at least one additional erase pulse to the group of non-volatile storage elements if the group of non-volatile storage elements are not sufficiently erased. - View Dependent Claims (8, 9, 10, 11, 12)
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13. A non-volatile storage device comprising:
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a plurality of bit lines; a plurality of NAND strings of non-volatile storage elements, the NAND strings are associated with the plurality of bit lines; a plurality of word lines associated with the non-volatile storage elements; and one or more managing circuits in communication with the plurality of NAND strings, the plurality of word lines, and the plurality of bit lines, the one or more managing circuits apply one or more erase pulses to the non-volatile storage elements, the one or more managing circuits apply one or more non-negative compare voltages to at least a portion of the plurality of word lines after applying the erase pulse, the one or more managing circuits sense conditions on the bit lines while holding differences between voltages on the bit lines substantially constant, the sensing is performed while applying the one or more compare voltages, the one or more managing circuits determine whether the NAND strings of non-volatile storage elements are sufficiently erased based on the conditions, the one or more managing circuits apply at least one additional erase pulse to the NAND strings of non-volatile storage elements if the NAND strings of non-volatile storage elements are not sufficiently erased. - View Dependent Claims (14, 15, 16, 17, 18, 19, 20, 21)
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22. A method for soft programming non-volatile storage in connection with an erase operation, the method comprising:
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erasing a group of non-volatile memory elements that are associated with a plurality of bit lines and a plurality of word lines; applying one or more non-negative compare voltages to at least a portion of the plurality of word lines as part of a soft programming operation after the erasing; allowing strong conduction currents of the plurality of bit lines to contribute to source line bias; sensing conditions of the bit lines, the sensing is performed while applying the one or more non-negative compare voltages and allowing the strong conduction currents to contribute to source line bias; and comparing threshold voltages of the non-volatile storage elements in the group to a target negative threshold voltage based on the conditions. - View Dependent Claims (23)
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24. A non-volatile storage device comprising:
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a plurality of NAND strings of non-volatile storage elements; a plurality of bit lines, the NAND strings are associated with the plurality of bit lines; a common source line the is coupled to the plurality of NAND strings; a plurality of word lines associated with the non-volatile storage elements; and
one or more managing circuits in communication with the plurality of NAND strings, the plurality of word lines, and the plurality of bit lines, the one or more managing circuits erase the non-volatile memory elements, the one or more managing circuits apply one or more non-negative compare voltages to at least a portion of the plurality of word lines as part of a soft programming operation after the erasing, the one or more managing circuits allow strong conduction currents of the plurality of bit lines to contribute to source line bias of the common source line, the one or more managing circuits sense conditions on the bit lines while applying the one or more non-negative compare voltages and while allowing the strong conduction currents to contribute to source line bias, the one or more managing circuits compare threshold voltages of the non-volatile storage elements to a target negative threshold voltage based on the sensed conditions. - View Dependent Claims (25)
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Specification