SEMICONDUCTOR DEVICE INCLUDING CONTACT PLUG HAVING AN ELLIPTICAL SECTIONAL SHAPE

• US 20100202208A1
• Filed: 02/03/2010
• Published: 08/12/2010
• Est. Priority Date: 02/06/2009
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: ENDO, MASATO, NITTA, HIROYUKI, KAWABATA, ITARU, WATANABE, SHINICHI, FUTATSUYAMA, TAKUYA
• Granted Patent: US 8,169,824 B2
• Time in Patent Office: Days
• US Class Current: 365/185.180
• CPC Class Codes: G11C 16/0466 comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: H01L 21/76816 Aspects relating to the layout of the pattern or to the size of vias or trenches layout of the interconnections per se H01L23/528; CAD of ICs G06F30/00
• CPC Class Codes: H01L 21/823871 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 29/41725 Source or drain electrodes for field effect devices with monocrystalline semiconductor on source/drain region H01L29/0843
• CPC Class Codes: H10B 41/10 characterised by the top-view layout
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND

Abstract

A semiconductor device includes a first MOS transistor, second MOS transistors, first contact plugs, and a second contact plug. The first MOS transistor with a first conductivity is formed on a semiconductor substrate. The second MOS transistors with a second conductivity are formed on the semiconductor substrate. The first contact plugs has a circular planar shape. The second contact plug has an elliptical planar shape and is formed on a source or a drain in one of the second MOS transistors. The first contact plugs are formed on sources or drains in the remaining second MOS transistors and the first MOS transistor.

Claims

1. A semiconductor device comprising:

a first MOS transistor with a first conductivity formed on a semiconductor substrate;

a plurality of second MOS transistors with a second conductivity formed on the semiconductor substrate;

a plurality of first contact plugs with a circular planar shape; and

a second contact plug with an elliptical planar shape formed on a source or a drain in one of the second MOS transistors, the first contact plugs being formed on sources or drains in the remaining second MOS transistors and the first MOS transistor.

2. The device according to claim 1, wherein the second contact plug is a single contact plug formed in each source or drain,

three of the first contact plugs are formed in each source or drain, and

in the gate width direction, the width of the source or drain of the one of the second MOS transistors in which the second contact plug is formed is less than the width of the source or drain of the first MOS transistor.

3. The device according to claim 1, wherein the second contact plug is a single contact plug formed in each source or drain,

one of the first contact plugs is formed in each source or drain, and

in the gate width direction, the width of the source or drain of the first MOS transistor is less than the width of the source or drain the second MOS transistor in which the second contact plug is formed.

4. The device according to claim 2, wherein the distance between the adjacent first contact plugs is greater than the planar diameter of the first contact plug.

5. The device according to claim 1, wherein the first conductivity is an N-type,

the second conductivity is a P-type, and

the source and the drain of the second MOS transistor include boron as an impurity.

6. The device according to claim 2, wherein a plane area of the one second contact plug is greater than the sum of plane areas of the three first contact plugs.

7. The device according to claim 1, further comprising:

a plurality of memory cell transistors formed on the semiconductor substrate and configured to store data;

a memory cell array in which the memory cell transistors are arrayed; and

a peripheral circuit configured to control a program operation, a read operation, and an erase operation on the memory cell array,

wherein the peripheral circuit includes the first MOS transistor and the second MOS transistors.

8. The device according to claim 1, further comprising:

a memory cell array including the first MOS transistor; and

a peripheral circuit configured to control a program operation, a read operation, and an erase operation on the memory cell array,

wherein the peripheral circuit includes the second MOS transistors.

9. The device according to claim 1, wherein one of the second MOS transistors in which the second contact plug is formed includes an impurity diffusion layer with the second conductivity between the source and the drain.

10. A semiconductor device comprising:

a first MOS transistor with a first conductivity formed on a semiconductor substrate;

a second MOS transistor with a second conductivity formed on the semiconductor substrate;

a third MOS transistor with the second conductivity formed on the semiconductor substrate;

a plurality of first contact plugs with a circular planar shape formed on sources or drains of the first and third MOS transistors; and

a second contact plug with an elliptical planar shape formed on a source or a drain of the second MOS transistor.

11. The device according to claim 10, wherein three of the first contact plugs are formed in each source or drain of the first MOS transistor, and

in the gate width direction, the width of the source or drain of the second MOS transistor is less than the width of the source or drain of the first MOS transistor.

12. The device according to claim 10, wherein one of the first contact plugs is formed in each source or drain of the first MOS transistor, and

in the gate width direction, the width of the source or drain of the second MOS transistor is greater than the width of the source or drain of the first MOS transistor.

13. The device according to claim 11, wherein the distance between the adjacent first contact plugs is greater than the planar diameter of the first contact plug.

14. The device according to claim 10, wherein the first conductivity is an N-type,

the second conductivity is a P-type, and

the source and the drain of the second MOS transistor include boron as an impurity.

15. The device according to claim 11, wherein a plane area of the second contact plug is greater than the sum of plane areas of the three of the first contact plugs.

16. The device according to claim 12, wherein three of the first contact plugs are formed in each source or drain of the third MOS transistor, and

in the gate width direction, the width of the source or drain of the second MOS transistor is less than the width of the source or drain of the third MOS transistor.

17. The device according to claim 10, further comprising:

a fourth MOS transistor with the first conductivity formed on the semiconductor substrate;

a fifth MOS transistor with the second conductivity formed on the semiconductor substrate; and

a plurality of the first contact plugs with the circular planar shape formed on sources or drains of the fourth and fifth MOS transistors,

wherein a gate insulating film of the fourth MOS transistor is greater than a gate insulating film of the first MOS transistor in film thickness, and

a gate insulating film of the fifth MOS transistor is greater than gate insulating films of the second and third MOS transistors in film thickness.

18. The device according to claim 11, further comprising:

a plurality of memory cell transistors formed on the semiconductor substrate and configured to store data;

a memory cell array in which the memory cell transistors are arrayed; and

a peripheral circuit configured to control a program operation, a read operation, and an erase operation on the memory cell array,

wherein the peripheral circuit includes the first to third MOS transistors, and

in the first MOS transistor, a plane area of each of contact plugs formed on the source or drain is minimum and the distance between the adjacent contact plugs is minimum among MOS transistors with the first conductivity included in the peripheral circuit.

19. The device according to claim 12, further comprising:

a plurality of memory cell transistors formed on the semiconductor substrate and configured to store data;

a memory cell array in which the memory cell transistors are arrayed; and

a peripheral circuit configured to control a program operation, a read operation, and an erase operation on the memory cell array,

wherein the peripheral circuit includes the first to third MOS transistors, and

in the first MOS transistor, a plane area of each of contact plugs formed on the source or drain is minimum and the distance between the adjacent contact plugs is minimum among MOS transistors with the first conductivity included in the peripheral circuit.