FLASH BACKED DRAM MODULE INCLUDING LOGIC FOR ISOLATING THE DRAM

• US 20100202238A1
• Filed: 02/11/2009
• Published: 08/12/2010
• Est. Priority Date: 02/11/2009
• Status: Active Grant

• Current Assignee: JP Morgan Chase Bank, N.A. (JP Morgan Chase & Co)
• Original Assignee: STEC Incorporated (Western Digital Corporation)
• Inventors: Moshayedi, Mark, Finke, Douglas
• Granted Patent: US 8,169,839 B2
• Time in Patent Office: Days
• US Class Current: 365/228
• CPC Class Codes: G06F 11/1658 Data re-synchronization of a redundant component, or initial sync of replacement, additional or spare unit
• CPC Class Codes: G06F 11/1666 where the redundant component is memory or memory area
• CPC Class Codes: G06F 11/2015 Redundant power supplies power supply failure G06F1/30
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/7203 Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks
• CPC Class Codes: G11C 16/30 Power supply circuits
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports
• CPC Class Codes: G11C 5/141 Battery and back-up supplies
• CPC Class Codes: G11C 5/143 Detection of memory cassette insertion or removal; Continuity checks of supply or ground lines; Detection of supply variations, interruptions or levels G11C5/148 takes precedence; Switching between alternative supplies G11C5/141 takes precedence
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A memory device for use with a primary power source including: non-volatile memory; volatile memory; an interface for connecting to a backup power source; isolation logic for controlling access to the volatile memory by a host processor, said isolation logic having a first mode during which the isolation logic provides the host processor with access to the volatile memory for storing or reading data and a second mode during which the isolation logic isolates the volatile memory from access by the host processor; and a controller controlling the isolation logic, said controller programmed to place the isolation logic in the first mode when the volatile memory is being powered by the primary power source and, when power to the volatile memory from the primary power source is interrupted, to place the isolation logic in the second mode and transfer data from the volatile memory to the non-volatile memory.

Claims

1. A memory device for use with a host processor and a primary power source, the memory device comprising:

non-volatile memory;

volatile memory;

an interface for connecting to a backup power source arranged to temporarily power the volatile memory upon a loss of power from the primary power source;

isolation logic for controlling access to the volatile memory by the host processor, said isolation logic having a first mode during which the isolation logic provides the host processor with access to the volatile memory for storing or reading data and a second mode during which the isolation logic isolates the volatile memory from access by the host processor; and

a controller controlling the isolation logic, said controller programmed to place the isolation logic in the first mode when the volatile memory is being powered by the primary power source and, when power to the volatile memory from the primary power source is interrupted, to place the isolation logic in the second mode and transfer data from the volatile memory to the non-volatile memory.

2. The memory device of claim 1, wherein the controller is further programmed to:

restore data from the non-volatile memory to the volatile memory upon a restoration of the primary power source; and

when the data is restored, place the isolation logic in the first mode.

3. The memory device of claim 1, wherein the controller is further programmed to drive a coupling between the controller and the isolation logic to a high impedance state when the isolation logic is in the first mode.

4. The memory device of claim 1, wherein in the isolation logic comprises at least one multiplexer.

5. The memory device of claim 1, wherein in the isolation logic comprises a first multiplexer arranged to multiplex address and control signals and a second multiplex arranged to multiplex data signals.

6. The memory device of claim 1, wherein the volatile memory comprises a dynamic random access memory.

7. The memory device of claim 1, wherein the non-volatile memory comprises electrically erasable programmable read-only memories (EEPROMs).

8. The memory device of claim 1, wherein the controller comprises at least one of an application-specific integrated circuit (ASIC) and a field programmable gate array (FPGA).

9. The memory device of claim 1, wherein power from the backup power source is primarily from a capacitor.

10. The memory device of claim 1, wherein power from the backup power source is primarily from a super capacitor.

11. A method comprising:

detecting a power failure of a primary power source of a volatile memory; and

in response to detecting the power failure and while the volatile memory is powered by a backup power source;

changing a mode of isolation logic from a first mode that provides a host processor with access to the volatile memory for storing or reading data when the volatile memory is being powered by the primary power source to a second mode that isolates the volatile memory from access by the host processor; and

moving data stored in the volatile memory to a non-volatile memory.

12. The method of claim 11, further comprising:

restoring data from the non-volatile memory to the volatile memory upon a restoration of the primary power source; and

when the data is restored, placing the isolation logic in the first mode.

13. The method of claim 11, further comprising drive a coupling between the controller and the isolation logic to a high impedance state when the isolation logic is in the first mode.

14. The method of claim 11, wherein in the isolation logic comprises at least one multiplexer.

15. The method of claim 11, wherein in the isolation logic comprises a first multiplexer arranged to multiplex address and control signals and a second multiplex arranged to multiplex data signals.

16. The method of claim 11, wherein the volatile memory comprises a dynamic random access memory.

17. The method of claim 11, wherein the non-volatile memory comprises electrically erasable programmable read-only memories (EEPROMs).

18. The method of claim 11, wherein power from the backup power source is primarily from a capacitor.

19. The method of claim 11, wherein power from the backup power source is primarily from a super capacitor.