STATE OF HEALTH MONITORED FLASH BACKED DRAM MODULE

• US 20100202240A1
• Filed: 02/11/2009
• Published: 08/12/2010
• Est. Priority Date: 02/11/2009
• Status: Active Grant

• Current Assignee: JP Morgan Chase Bank, N.A. (JP Morgan Chase & Co)
• Original Assignee: STEC Incorporated (Western Digital Corporation)
• Inventors: MOSHAYEDI, Mark, Finke, Douglas
• Granted Patent: US 7,990,797 B2
• Time in Patent Office: Days
• US Class Current: 365/229
• CPC Class Codes: G06F 11/1441 Resetting or repowering
• CPC Class Codes: G06F 12/0802 Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
• CPC Class Codes: G06F 2212/1032 Reliability improvement, data loss prevention, degraded operation etc
• CPC Class Codes: G11C 16/22 Safety or protection circuits preventing unauthorised or accidental access to memory cells
• CPC Class Codes: G11C 16/30 Power supply circuits
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports
• CPC Class Codes: G11C 5/141 Battery and back-up supplies
• CPC Class Codes: G11C 5/143 Detection of memory cassette insertion or removal; Continuity checks of supply or ground lines; Detection of supply variations, interruptions or levels G11C5/148 takes precedence; Switching between alternative supplies G11C5/141 takes precedence
• CPC Class Codes: G11C 5/147 Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops G11C5/141 takes precedence
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A device includes: non-volatile memory; a controller in communication with the non-volatile memory, wherein the controller is programmed to move data from a volatile memory to the non-volatile memory upon a loss of power of a primary power source of the volatile memory; and a backup power supply providing temporary power to the controller and the volatile memory upon the loss of power of the primary power source, including: a capacitor bank with an output terminal; a connection to a voltage source that charges the capacitor bank to a normal operating voltage; and a state-of-health monitor that is programmed to generate a failure signal based on a voltage at the output terminal of the capacitor bank.

Claims

1. A device comprising:

non-volatile memory;

a controller in communication with the non-volatile memory, wherein the controller is programmed to move data from a volatile memory to the non-volatile memory upon a loss of power of a primary power source of the volatile memory; and

a backup power supply providing temporary power to the controller and the volatile memory upon the loss of power of the primary power source, comprising;

a capacitor bank with an output terminal;

a connection to a voltage source that charges the capacitor bank to a normal operating voltage; and

a state-of-health monitor that is programmed to generate a failure signal based on a voltage at the output terminal of the capacitor bank.

2. The memory device of claim 1, where the state-of-health monitor is further programmed to:

interrupt the charging of the capacitor bank by the voltage source;

while the charging is interrupted, apply a predetermined resistance across the output terminal of the capacitor bank for a predetermined period of time;

monitor the output terminal of the capacitor bank during the predetermined period of time to determine whether the voltage at the output terminal falls below a predetermined threshold voltage; and

if the voltage at the output terminal falls below the predetermined threshold voltage within the predetermined period of time, generate the failure signal.

3. The memory device of claim 2, wherein the predetermined resistance and predetermined time are determined to keep the voltage across the output terminal of the capacitor above a necessary operating voltage.

4. The memory device of claim 1, wherein the capacitor bank comprises a plurality of capacitors in parallel.

5. The memory device of claim 4, further comprising a capacitor-level terminal at each capacitor of the plurality of capacitors and wherein the state-of-health monitor that is further programmed to generate the failure signal based on a voltage at any of the capacitor-level terminals.

6. The memory device of claim 1, further comprising:

a processor in communication with the volatile memory and a permanent storage system, wherein, if the failure signal is generated by the controller, the processor is programmed to move the data from the volatile memory to the permanent storage system.

7. The memory device of claim 6, where in the permanent storage system comprises a hard drive.

8. The memory device of claim 1, wherein the volatile memory comprises a dynamic random access memory.

9. The memory device of claim 1, wherein the non-volatile memory comprises electrically erasable programmable read-only memories (EEPROMs).

10. The memory device of claim 1, wherein the controller comprises at least one of an application-specific integrated circuit (ASIC) and a field programmable gate array (FPGA).

11. The memory device of claim 1, wherein, the controller is further programmed to move data from the non-volatile memory to the volatile memory upon a restoration of power of the primary power source.

12. The memory device of claim 1, wherein the controller and the backup power supply are in communication through a configuration data bus.

13. The memory device of claim 11, wherein the configuration data bus is an I2C bus.

14. A method comprising:

interrupting the charging, by a voltage source, of a capacitor bank arranged to provide temporary power to a controller programmed to move data from a volatile memory to a non-volatile memory upon a loss of power of a primary power source of the volatile memory and to provide power to a volatile memory upon the loss of power of a primary power source;

while the charging is interrupted, applying a predetermined resistance across the output terminal of the capacitor bank for a predetermined period of time;

monitoring the output terminal of the capacitor bank during the predetermined period of time to determine whether the voltage at the output terminal falls below a predetermined threshold voltage; and

if the voltage at the output terminal falls below the predetermined threshold voltage within the predetermined period of time, generating a failure signal.

15. The method of claim 14, wherein the predetermined resistance and predetermined time are determined to keep the voltage across the output terminal of the capacitor above a necessary operating voltage.

16. The method of claim 14, wherein the capacitor bank comprises a plurality of capacitors in parallel.

17. The method of claim 14, wherein there is a capacitor-level terminal at each capacitor of the plurality of capacitors and further comprising generating the failure signal based on a voltage at any of the capacitor-level terminals.

18. The method of claim 17, wherein the failure signal indicates which of the plurality capacitors has failed.

19. The method of claim 14, wherein the non-volatile memory comprises electrically erasable programmable read-only memories (EEPROMs).

20. The method of claim 14, wherein the controller comprises at least one of an application-specific integrated circuit (ASIC) and a field programmable gate array (FPGA).