Highly Integrated Media Access Control

• US 20100202457A1
• Filed: 04/20/2010
• Published: 08/12/2010
• Est. Priority Date: 09/27/2001
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Pantelias, Niki Roberta, Denney, Lisa Voigt, Nazareth, Sean Francis, Horton, John Daniel JR., Moshar, Hooman, Lansing, Shane Patrick
• Granted Patent: US 7,991,010 B2
• Time in Patent Office: Days
• US Class Current: 370/392
• CPC Class Codes: H04L 12/2801 Broadband local area networks
• CPC Class Codes: H04L 47/50 Queue scheduling
• CPC Class Codes: H04L 47/52 by attributing bandwidth to queues
• CPC Class Codes: H04L 47/6215 Individual queue per QOS, rate or priority
• CPC Class Codes: H04L 49/9094 Arrangements for simultaneous transmit and receive, e.g. simultaneous reading/writing from/to the storage element
• CPC Class Codes: H04L 69/22 Parsing or analysis of headers
• CPC Class Codes: H04N 7/17309 Transmission or handling of upstream communications

Abstract

A supervisory communications device, such as a headend device within a communications network, monitors and controls communications with a plurality of remote communications devices throughout a widely distributed network. The supervisory device allocates bandwidth on the upstream channels by sending MAP messages over its downstream channel. A highly integrated media access controller integrated circuit (MAC IC) operates within the headend to provide lower level processing on signals exchanged with the remote devices. The enhanced functionality of the MAC IC relieves the processing burden on the headend CPU and increases packet throughput. The enhanced functionality includes header suppression and expansion, DES encryption and decryption, fragment reassembly, concatenation, and DMA operations

Claims

1. An apparatus to process an egress signal within a media access controller integrated circuit (MAC IC), comprising:

an egress postprocessor configured to process a frame of data, the egress postprocessor comprises;

a header postprocessor configured to deconcatenate a header from the frame of data,

a payload header suppression/expansion (PHS) processor configured to expand a payload header suppressed packet from the header based upon one or more PHS rules to provide an expanded frame of data.

2. The apparatus of claim 1, wherein the egress postprocessor further comprises:

a packet direct memory access (DMA) module configured to send the expanded frame of data for storage in a memory.

3. The apparatus of claim 2, further comprising:

an egress memory controller configured to receive the expanded frame of data and to deliver the expanded frame of data to the memory.

4. The apparatus of claim 3, further comprising:

an input/output (I/O) arbitrator configured to receive the expanded frame of data from the memory and to provide the expanded frame of data to a software application.

5. The apparatus of claim 2, wherein the header postprocessor is further configured to receive the frame of data from a first bus, and wherein the packet DMA module is further configured to send expanded frame of data over a second bus to be stored in the memory, the first bus being different from the second bus.

6. The apparatus of claim 1, wherein the PHS processor is further configured to expand the payload header suppressed packet according to Data Over Cable Service Interface Specification (DOCSIS) Payload Header Suppression.

7. The apparatus of claim 1, further comprising:

a fragment reassembly controller configured to identify a fragmented frame from a payload of the egress signal and to reassemble one or more fragmented frames to provide the frame of data.

8. The apparatus of claim 7, further comprising:

an egress pre-processor configured to perform preliminary signal processing on the egress signal to provide the payload.

9. The apparatus of claim 7, further comprising:

an egress memory controller configured to deliver the frame of data to a memory and to provide the frame of data from the memory to the header postprocessor.

10. The apparatus of claim 1, wherein the PHS processor is further configured to receive the one or more PHS rules from a memory.

11. A method for processing an egress signal within a media access controller integrated circuit (MAC IC), comprising:

(a) deconcatenating, by a header postprocessor, a header from a frame of data; and

(b) expanding, by a payload header suppression/expansion (PHS) processor, a payload header suppressed packet from the header based upon one or more PHS rules to provide an expanded frame of data.

12. The method of claim 11, further comprising:

(c) sending, by a packet direct memory access (DMA) module, the expanded frame of data for storage in a memory.

13. The method of claim 12, further comprising:

(c) receiving, by an egress memory controller, the expanded frame of data; and

(d) delivering, by the egress memory controller, the expanded frame of data to the memory.

14. The method of claim 13, further comprising:

(e) receiving, by an input/output (I/O) arbitrator, the expanded frame of data from the memory; and

(f) providing, by the I/O arbitrator, the expanded frame of data to a software application

15. The method of claim 12, wherein step (a) comprises:

(a)(i) receiving, by a header postprocessor, the header from a first bus, and

wherein step (c) comprises;

(c)(i) sending, by the packet DMA module, the expanded frame of data over a second bus for storage in a memory, the first bus being different from the second bus.

16. The method of claim 11, wherein step (b) comprises:

(b)(i) expanding, by the PHS processor, the payload header suppressed packet according to Data Over Cable Service Interface Specification (DOCSIS) Payload Header Suppression.

17. The method of claim 11, further comprising:

(c) identifying, by a fragment reassembly controller, a fragmented frame from a payload of the egress signal and to reassemble one or more fragmented frames to provide the frame of data.

18. The method of claim 17, further comprising:

(d) performing, by an egress pre-processor, preliminary signal processing on the egress signal to provide the payload.

19. The method of claim 17, further comprising:

(d) delivering, by an egress memory controller, the frame of data to a memory; and

(c) providing, by the egress memory controller, the frame of data from the memory to the header postprocessor.

20. The method of claim 11, wherein step (b) comprises:

(b)(i) receiving the one or more PHS rules from a memory.