MICROPHONE AND INTEGRATED CIRCUIT CAPIBLE OF ECHO CANCELLATION

• US 20100202634A1
• Filed: 02/06/2009
• Published: 08/12/2010
• Est. Priority Date: 02/06/2009
• Status: Active Grant

• Current Assignee: Fortemedia, Inc.
• Original Assignee: Fortemedia, Inc.
• Inventors: Wu, Li-Te
• Granted Patent: US 8,064,619 B2
• Time in Patent Office: Days
• US Class Current: 381/111
• CPC Class Codes: H04R 3/02 for preventing acoustic reaction , i.e. acoustic oscillatory feedback specially adapted for hearing aids H04R25/453

Abstract

The invention provides an integrated circuit of a microphone. In one embodiment, the integrated circuit receives a first signal converted from a sound and receives a reference signal with a digital format for echo cancellation. In one embodiment, the integrated circuit comprises a pre-amplifier, an analog-to-digital converter, a digital signal processor, and a post amplifier. The pre-amplifier amplifies the first signal according to a first gain to obtain a third signal. The analog-to-digital converter converts the third signal from analog to digital to obtain a fourth signal. The digital signal processor cancels an echo component from the fourth signal according to the reference signal to obtain a fifth signal, and determines the first gain and a second gain, wherein a product of the first gain and the second gain is kept constant, and the first gain is determined so that an amplitude of the third signal is kept equal to an amplitude of the reference signal. The post-amplifier amplifies the fifth signal according to the second gain to obtain a second signal as an output of the integrated circuit.

Claims

1. A microphone, comprising:

a microphone cartridge, receiving a sound and converting the sound to a first signal;

an integrated circuit, coupled to the microphone cartridge, receiving a reference signal from a baseband processor, canceling an echo component from the first signal according to the reference signal to obtain a second signal, and outputting the second signal to the baseband processor, wherein the reference signal has a digital format and is sent from a remote side;

wherein a data line is coupled between the integrated circuit and the baseband processor, and the integrated circuit receives the reference signal and outputs the second signal via a data line.

2. The microphone as claimed in claim 1, wherein the integrated circuit comprises:

a pre-amplifier, amplifying the first signal according to a first gain to obtain a third signal;

an analog-to-digital converter, converting the third signal from analog to digital to obtain a fourth signal;

a digital signal processor, canceling an echo component from the fourth signal according to the reference signal to obtain a fifth signal, and determining the first gain and a second gain, wherein a product of the first gain and the second gain is kept constant, and the first gain is determined so that an amplitude of the third signal is kept equal to an amplitude of the reference signal; and

a post-amplifier, amplifying the fifth signal according to the second gain to obtain the second signal

3. The microphone as claimed in claim 1, wherein the baseband processor provides the integrated circuit with a clock signal, and the integrated circuit comprises a data interface, outputting the second signal to the data line at a falling edge of the clock signal, and receiving the reference signal from the data line at a rising edge of the clock signal.

4. The microphone as claimed in claim 1, wherein the baseband processor provides the integrated circuit with a clock signal, and the integrated circuit comprises a data interface, outputting the second signal to the data line at a prior cycle of the clock signal, and reading the reference signal from the data line at a subsequent cycle of the clock signal.

5. The microphone as claimed in claim 2, wherein the digital signal processor comprises:

an adaptive filter, determining a filter coefficient set according to the fifth signal, and filtering the reference signal according to the filter coefficient set to obtain a filtered reference signal;

a first power estimator, calculating a first power of the reference signal;

a second power estimator, calculating a second power of the filtered reference signal;

a gain controller, increasing the first gain when the first power is greater than the second power, and decreasing the first gain when the first power is less than the second power; and

a subtractor, subtracting the filtered reference signal from the fourth signal to obtain the fifth signal.

6. The microphone as claimed in claim 5, wherein the adaptive filter determines the filter coefficient set according to the following algorithm:

{right arrow over (W)}(n+1)={right arrow over (W)}(n)+μ

·

V(n)·

{right arrow over (X)}(n); and

{right arrow over (X)}(n)=[V(n),V(n−

1), . . . ,V(n−

N)],

wherein n is a sample index, W is the filter coefficient set, V is the fifth signal, and μ

is a predetermined value.

7. The microphone as claimed in claim 5, wherein the first power estimator calculates the first power according to the following algorithm:

P₁(n+1)=α

₁·

P₁(n)+(1−

α

₁)·

Q₁(n),

wherein n is a sample index, P₁ is the first power, α

₁ is a predetermined value, and Q₁ is a current power of the reference signal; and

the second power estimator calculates the second power according to the following algorithm;

P₂(n+1)=α

₂·

P₂(n)+(1−

α

₂)·

Q₂(n),

wherein n is a sample index, P₂ is the second power, α

₂ is a predetermined value, and Q₂ is a current power of the filtered reference signal.

8. The microphone as claimed in claim 5, wherein the gain controller adjusts the first gain and the second gain according to the following algorithm when the first power is greater than the second power:

G₁(n+1)=G₁(n)·

Δ

G;

and

G₂(n+1)=G₂(n)/Δ

G,

wherein n is a sample index, G₁ is the first gain, G₂ is the second gain, and Δ

G is a minimum gain step size; and

the gain controller adjusts the first gain and the second gain according to the following algorithm when the first power is less than the second power;

G₁(n+1)=G₁(n)/Δ

G;

and

G₂(n+1)=G₂(n)·

Δ

G,

wherein n is a sample index, G₁ is the first gain, G₂ is the second gain, and Δ

G is the minimum gain step size.

9. The microphone as claimed in claim 8, wherein the gain controller adjusts the filter coefficient set according to the following algorithm when the first power is greater than the second power:

{right arrow over (W)}(n+1)={right arrow over (W)}(n)·

Δ

G,

wherein n is a sample index, W is the filter coefficient set, and Δ

G is the minimum gain step size; and

the gain controller adjusts the filter coefficient set according to the following algorithm when the first power is less than the second power;

{right arrow over (W)}(n+1)={right arrow over (W)}(n)/Δ

G,

wherein n is a sample index, W is the filter coefficient set, G₂ is the second gain, and Δ

G is the minimum gain step size.

10. The microphone as claimed in claim 5, wherein the gain controller increases the filter coefficient set when the first power is greater than the second power, and decreases the filter coefficient set when the first power is less than the second power.

11. An integrated circuit of a microphone, wherein the integrated circuit receives a first signal converted from a sound and receives a reference signal with a digital format for echo cancellation, comprising:

a pre-amplifier, amplifying the first signal according to a first gain to obtain a third signal;

an analog-to-digital converter, converting the third signal from analog to digital to obtain a fourth signal;

a digital signal processor, canceling an echo component from the fourth signal according to the reference signal to obtain a fifth signal, and determining the first gain and a second gain, wherein a product of the first gain and the second gain is kept constant, and the first gain is determined so that an amplitude of the third signal is kept equal to an amplitude of the reference signal; and

a post-amplifier, amplifying the fifth signal according to the second gain to obtain a second signal as an output of the integrated circuit.

12. The integrated circuit as claimed in claim 11, wherein the digital signal processor comprises:

an adaptive filter, determining a filter coefficient set according to the fifth signal, and filtering the reference signal according to the filter coefficient set to obtain a filtered reference signal;

a first power estimator, calculating a first power of the reference signal;

a second power estimator, calculating a second power of the filtered reference signal;

a gain controller, increasing the first gain when the first power is greater than the second power, and decreasing the first gain when the first power is less than the second power; and

a subtractor, subtracting the filtered reference signal from the fourth signal to obtain the fifth signal.

13. The integrated circuit as claimed in claim 12, wherein the adaptive filter determines the filter coefficient set according to the following algorithm:

{right arrow over (W)}(n+1)={right arrow over (W)}(n)+μ

·

V(n)·

{right arrow over (X)}(n); and

{right arrow over (X)}(n)=[V(n),V(n−

1), . . . ,V(n−

N)],

wherein n is a sample index, W is the filter coefficient set, V is the fifth signal, and μ

is a predetermined value.

14. The integrated circuit as claimed in claim 12, wherein the first power estimator calculates the first power according to the following algorithm:

P₁(n+1)=α

₁·

P₁(n)+(1−

α

₁)·

Q₁(n),

wherein n is a sample index, P₁ is the first power, α

₁ is a predetermined value, and Q₁ is a current power of the reference signal; and

the second power estimator calculates the second power according to the following algorithm;

P₂(n+1)=α

₂·

P₂(n)+(1−

α

₂)·

Q₂(n),

wherein n is a sample index, P₂ is the second power, α

₂ is a predetermined value, and Q₂ is a current power of the filtered reference signal.

15. The integrated circuit as claimed in claim 12, wherein the gain controller adjusts the first gain and the second gain according to the following algorithm when the first power is greater than the second power:

G₁(n+1)=G₁(n)·

Δ

G;

and

G₂(n+1)=G₂(n)/Δ

G,

wherein n is a sample index, G₁ is the first gain, G₂ is the second gain, and Δ

G is a minimum gain step size; and

the gain controller adjusts the first gain and the second gain according to the following algorithm when the first power is less than the second power;

G₁(n+1)=G₁(n)/Δ

G;

and

G₂(n+1)=G₂(n)·

Δ

G,

wherein n is a sample index, G₁ is the first gain, G₂ is the second gain, and Δ

G is the minimum gain step size.

16. The integrated circuit as claimed in claim 15, wherein the gain controller adjusts the filter coefficient set according to the following algorithm when the first power is greater than the second power:

{right arrow over (W)}(n+1)={right arrow over (W)}(n)·

Δ

G,

wherein n is a sample index, W is the filter coefficient set, and Δ

G is the minimum gain step size; and

the gain controller adjusts the filter coefficient set according to the following algorithm when the first power is less than the second power;

{right arrow over (W)}(n+1)={right arrow over (W)}(n)/Δ

G,

wherein n is a sample index, W is the filter coefficient set, G₂ is the second gain, and Δ

G is the minimum gain step size.

17. The integrated circuit as claimed in claim 12, wherein the gain controller increases the filter coefficient set when the first power is greater than the second power, and decreases the filter coefficient set when the first power is less than the second power.

18. The integrated circuit as claimed in claim 12, wherein a data line is coupled between the integrated circuit and a baseband processor, the baseband processor provides the integrated circuit with a clock signal and the reference signal via the data line and receives the second signal from the integrated circuit via the data line.

19. The integrated circuit as claimed in claim 18, wherein the integrated circuit comprises a data interface, outputting the second signal to the data line at a falling edge of the clock signal, and receiving the reference signal from the data line at a rising edge of the clock signal.

20. The integrated circuit as claimed in claim 18, wherein the integrated circuit comprises a data interface, outputting the second signal to the data line at a prior cycle of the clock signal, and reading the reference signal from the data line at a subsequent cycle of the clock signal.