FLASH BACKED DRAM MODULE STORING PARAMETER INFORMATION OF THE DRAM MODULE IN THE FLASH

• US 20100205348A1
• Filed: 02/11/2009
• Published: 08/12/2010
• Est. Priority Date: 02/11/2009
• Status: Active Grant

• Current Assignee: JP Morgan Chase Bank, N.A. (JP Morgan Chase & Co)
• Original Assignee: STEC Incorporated (Western Digital Corporation)
• Inventors: MOSHAYEDI, Mark, Finke, Douglas
• Granted Patent: US 8,977,831 B2
• Time in Patent Office: Days
• US Class Current: 711/102
• CPC Class Codes: G06F 1/30 Means for acting in the event of power-supply failure or interruption, e.g. power-supply fluctuations for resetting only G06F1/24
• CPC Class Codes: G06F 1/3296 by lowering the supply or operating voltage
• CPC Class Codes: G06F 11/0727 in a storage system, e.g. in a DASD or network based storage system drivers for digital recording or reproducing units G06F3/06; circuits for error detection or correction within digital recording or reproducing units G11B20/18; for distributed storage of data in networks, e.g. transport arrangements for network file system [NFS], storage area networks [SAN] or network attached storage [NAS], H04L67/1097
• CPC Class Codes: G06F 11/1402 Saving, restoring, recovering or retrying
• CPC Class Codes: G06F 3/0625 Power saving in storage systems
• CPC Class Codes: G06F 3/0634 by changing the state or mode of one or more devices
• CPC Class Codes: G06F 3/0655 Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays
• CPC Class Codes: G11C 14/0018 whereby the nonvolatile element is an EEPROM element, e.g. a floating gate or metal-nitride-oxide-silicon [MNOS] transistor
• CPC Class Codes: G11C 5/14 Power supply arrangements , e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
• CPC Class Codes: G11C 5/141 Battery and back-up supplies
• CPC Class Codes: G11C 5/143 Detection of memory cassette insertion or removal; Continuity checks of supply or ground lines; Detection of supply variations, interruptions or levels G11C5/148 takes precedence; Switching between alternative supplies G11C5/141 takes precedence

Abstract

A device includes volatile memory; one or more non-volatile memory chips, each of which is for storing data moved from the volatile-memory; an interface for connecting to a backup power source arranged to temporarily power the volatile memory upon a loss of power from a primary power source; a controller in communication with the volatile memory and the non-volatile memory, wherein: the controller is programmed to move data from the volatile memory to the non-volatile memory chips upon a loss of power of the primary power source of the volatile memory; and parameters describing the volatile memory are stored in at least one of the non-volatile memory chips that store the data moved from the volatile memory. In some aspects the parameters include serial presence detect information.

Claims

1. A device comprising:

volatile memory;

one or more non-volatile memory chips, each of which is for storing data moved from the volatile-memory;

an interface for connecting to a backup power source arranged to temporarily power the volatile memory upon a loss of power from a primary power source;

a controller in communication with the volatile memory and the non-volatile memory,

wherein;

the controller is programmed to move data from the volatile memory to the non-volatile memory chips upon a loss of power of the primary power source of the volatile memory; and

parameters describing the volatile memory are stored in at least one of the non-volatile memory chips that store the data moved from the volatile memory.

2. The memory device of claim 1, wherein the parameters comprise serial presence detect information.

3. The memory device of claim 1, where the parameters describe a size of the volatile memory.

4. The memory device of claim 1, where the parameters describe a speed of the volatile memory.

5. The memory device of claim 1, wherein the controller further comprises a cache for storing the parameters.

6. The memory device of claim 1, further comprising a configuration data bus for accessing the parameters.

7. The memory device of claim 1, further comprising a configuration data bus for accessing the parameters, wherein the controller further comprises a cache for storing the parameters, and wherein the controller is further programmed to read the parameters from the cache in response to receiving a request for the parameters over the configuration data bus.

8. The memory device of claim 1, wherein the volatile memory comprises a dynamic random access memory.

9. The memory device of claim 1, wherein the non-volatile memory chips comprise electrically erasable programmable read-only memory.

10. The memory device of claim 1, wherein the controller comprises at least one of an application-specific integrated circuit (ASIC) and a field programmable gate array (FPGA).

11. The memory device of claim 1, wherein the controller is further programmed to move data from the non-volatile memory chips to the volatile memory upon a restoration of power of the primary power source.

12. The memory device of claim 1, wherein power from the backup power source is primarily from a capacitor.

13. The memory device of claim 1, wherein power from the backup power source is primarily from a super capacitor.

14. A method comprising:

moving data from a volatile memory to non-volatile memory chips, each of which is for storing data moved from the volatile-memory, upon a loss of power of a primary power source of the volatile memory based on parameters describing the volatile memory stored in at least one of the non-volatile memory chips that store the data moved from the volatile memory while the volatile memory is temporarily powered by a backup power source.

15. The method of claim 14, wherein the parameters comprise serial presence detect information.

16. The method of claim 14, where the parameters describe a size of the volatile memory.

17. The method of claim 14, where the parameters describe a speed of the volatile memory.

18. The method of claim 14, further comprising moving data from the non-volatile memory chips to the volatile memory upon a restoration of power of the primary power source.

19. The method of claim 14, wherein power from the backup power source is primarily from a capacitor.

20. The method of claim 14, wherein the non-volatile memory chips comprise electrically erasable programmable read-only memory.