MULTILEVEL CELL NAND FLASH MEMORY STORAGE SYSTEM, AND CONTROLLER AND ACCESS METHOD THEREOF
First Claim
1. A multi level cell (MLC) NAND flash memory storage system, for simulating a single level cell (SLC) NAND flash memory chip, the MLC NAND flash memory storage system comprising:
- a connector, for connecting a host system;
a MLC NAND flash memory chip, having a plurality of MLC physical blocks, wherein each of the MLC physical blocks has a plurality of pages; and
a flash memory controller, coupled to the MLC NAND flash memory chip and the connector, for providing a plurality of SLC logical blocks corresponding to the SLC NAND flash memory chip to the host system, wherein each of the MLC physical blocks is mapped to at least two of the SLC logical blocks.
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Accused Products
Abstract
A multi level cell (MLC) NAND flash memory storage system is provided. A controller of the MLC NAND flash memory storage system declares it a signal level cell (SLC) NAND flash memory chip to a host system connected thereto and provides a plurality of SLC logical blocks to the host system. When the controller receives a write command and a user data from the host system, the controller writes the user data into a page of a MLC physical block and records the page of the SLC logical block corresponding to the page of the MLC physical block. When the controller receives an erase command from the host system, the controller writes a predetermined data into the page of the MLC physical block mapped to the SLC logical block to be erased, wherein the predetermined data has the same pattern as a pattern of the erased page.
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Citations
32 Claims
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1. A multi level cell (MLC) NAND flash memory storage system, for simulating a single level cell (SLC) NAND flash memory chip, the MLC NAND flash memory storage system comprising:
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a connector, for connecting a host system; a MLC NAND flash memory chip, having a plurality of MLC physical blocks, wherein each of the MLC physical blocks has a plurality of pages; and a flash memory controller, coupled to the MLC NAND flash memory chip and the connector, for providing a plurality of SLC logical blocks corresponding to the SLC NAND flash memory chip to the host system, wherein each of the MLC physical blocks is mapped to at least two of the SLC logical blocks. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A flash memory controller, suitable for simulating a MLC NAND flash memory chip into a SLC NAND flash memory chip, wherein the MLC NAND flash memory chip has a plurality of MLC physical blocks and each of the MLC physical blocks has a plurality of pages, the flash memory controller comprising:
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a microprocessor unit, coupled to a first flash memory interface and a second flash memory interface; a SLC block simulation unit, coupled to the microprocessor unit, for providing a plurality of SLC logical blocks corresponding to the SLC NAND flash memory chip to a host system, wherein each of the MLC physical blocks is mapped to at least two of the SLC logical blocks; a first flash memory interface unit, coupled to the microprocessor unit, for receiving a logical address and a command corresponding to the SLC logical blocks from the host system and providing the logical address and the command to the microprocessor unit; and a second flash memory interface unit, coupled to the microprocessor unit, for electrically connecting the MLC NAND flash memory. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22)
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23. An access method, for simulating a MLC NAND flash memory chip into a SLC NAND flash memory chip, the access method comprising:
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providing the MLC NAND flash memory chip, wherein the MLC NAND flash memory chip has a plurality of MLC physical blocks and each of the MLC physical blocks has a plurality of pages; disposing a plurality of SLC logical blocks; recording a mapping relationship between the MLC physical blocks and the SLC logical blocks, wherein each of the MLC physical blocks is mapped to at least two of the SLC logical blocks; and writing data into the MLC physical blocks and reading the data from the MLC physical blocks according to the mapping relationship. - View Dependent Claims (24, 25, 26, 27, 28, 29, 30, 31, 32)
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Specification