MEMORY CONTROLLER, MEMORY SYSTEM WITH MEMORY CONTROLLER, AND METHOD OF CONTROLLING FLASH MEMORY

• US 20100205357A1
• Filed: 02/08/2010
• Published: 08/12/2010
• Est. Priority Date: 02/09/2009
• Status: Active Grant

• Current Assignee: TDK Corporation
• Original Assignee: TDK Corporation
• Inventors: MUKAIDA, Naoki
• Granted Patent: US 8,200,892 B2
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G06F 2212/7202 Allocation control and policies
• CPC Class Codes: G06F 2212/7211 Wear leveling

Abstract

In the control of the number of program-erase cycles, when assigning a logical block (LB) to a physical block (PB), the number of program-erase cycles of a first PB and that of a second PB are compared, which first PB is a free PB of which the number of program-erase cycles is the smallest among that of free PBs, which second PB is a PB earliest assigned a LB among PBs each assigned a LB. As a result, in a case where the number of program-erase cycles of the first PB is larger by a predetermined value or more than that of the second PB, data stored in the second PB are transferred to a free PB of which the number of program-erase cycles is the largest among free PBs, and then the LB is assigned to the second PB.

Claims

1. A memory controller for controlling access to one or more flash memories, in which data erasing is performed in physical blocks, comprising:

a logical block management unit which forms plural logical blocks each composed of plural logical sectors to each of which a logical address for a host system is assigned;

a program-erase cycles management unit which manages a number of program-erase cycles of each physical block;

a first search unit which searches out a first physical block and a second physical block, which first physical block is a free physical block of which the number of program-erase cycles is the smallest among free physical blocks, which second physical block is a free physical block of which the number of program-erase cycles is the largest among free physical blocks;

a assignment unit which assigns a logical block to a physical block, which logical block is composed of plural logical sectors to each of which a logical address for a host system is assigned;

a second search unit which searches out a third physical block to which a logical block is assigned earliest among physical blocks to each of which a logical block is assigned;

a data writing unit which, in response to a request issued by the host system, identifies a logical block including a logical sector corresponding to a logical address pertaining to the request and stores data provided from the host system in a physical block corresponding to the logical block identified;

a determination unit which makes a determination whether or not the number of program-erase cycles of the first physical block is larger by a predetermined value or more than the number of program-erase cycles of the third physical block; and

a data transfer unit which performs data transfer for transferring data stored in the third physical block to the second physical block;

wherein, when the assignment unit assigns a logical block to a physical block, the determination unit makes the determination; and

wherein, in a case where the determination is positive, the assignment unit assigns the logical block to the third physical block after completing the data transfer,

wherein, in a case where the determination is negative, the assignment unit assigns the logical block to the first physical block.

3. A memory system comprising:

a memory controller according to claim 1; and

one or more flash memories to which access is controlled by the memory controller.

2. A memory controller for controlling access to one or more flash memories, in which data erasing is performed in physical blocks, comprising:

a logical block management unit which forms plural logical blocks each composed of plural logical sectors to each of which a logical address for a host system is assigned;

a virtual block management unit which forms plural virtual blocks into which physical blocks are divided;

a program-erase cycles management unit which manages the number of program-erase cycles of each virtual block;

a first search unit which searches out a first virtual block and a second virtual block, which first virtual block is a free virtual block of which the number of program-erase cycles is the smallest among free virtual blocks, which second virtual block is a free virtual block of which a number of program-erase cycles is the largest among free virtual blocks;

a assignment unit which assigns a logical block to a virtual block which logical block is composed of plural logical sectors to each of which a logical address for a host system is assigned;

a second search unit which searches out a third virtual block to which a logical block is assigned earliest among virtual blocks to each of which a logical block is assigned;

a data writing unit which, in response to a request issued by the host system, identifies a logical block including a logical sector corresponding to a logical address pertaining to the request and stores data provided from the host system in a virtual block corresponding to the logical block identified;

a determination unit which makes a determination whether or not the number of program-erase cycles of the first virtual block is larger by a predetermined value or more than the number of program-erase cycles of the third virtual block; and

a data transfer unit which performs data transfer for transferring data stored in the third virtual block to the second virtual block;

wherein, when the assignment unit assigns a logical block to a virtual block, the determination unit makes the determination; and

wherein, in a case where the determination is positive, the assignment unit assigns the logical block to the third virtual block after completing the data transfer,

wherein, in a case where the determination is negative, the assignment unit assigns the logical block to the first physical block.

4. A memory system comprising:

a memory controller according to claim 2; and

one or more flash memories to which access is controlled by the memory controller.

5. A method for controlling access to one or more flash memories, in which data erasing is performed in physical blocks, comprising:

a logical block management step of forming plural logical blocks each composed of plural logical sectors to each of which a logical address for a host system is assigned;

a program-erase cycles management step of managing a number of program-erase cycles of each physical block;

a first search step of searching out a first physical block and a second physical block, which first physical block is a free physical block of which the number of program-erase cycles is the smallest among free physical blocks, which second physical block is a free physical block of which the number of program-erase cycles is the largest among free physical blocks;

a assignment step of assigning a logical block to a physical block, which logical block is composed of plural logical sectors to each of which a logical address for a host system is assigned;

a second search step of searching out a third physical block to which a logical block is assigned earliest among physical blocks to each of which a logical block is assigned;

a data writing step of, in response to a request issued by the host system, identifying a logical block including a logical sector corresponding to a logical address pertaining to the request and stores data provided from the host system in a physical block corresponding to the logical block identified;

a determination step of making a determination whether or not the number of program-erase cycles of the first physical block is larger by a predetermined value or more than the number of program-erase cycles of the third physical block; and

a data transfer step of performing data transfer for transferring data stored in the third physical block to the second physical block;

wherein, when assigning a logical block to a physical block in the assignment step, making the determination in the determination step; and

wherein, in a case where the determination is positive, assigning the logical block to the third physical block, in the assignment step, after completing the data transfer,

wherein, in a case where the determination is negative, assigning the logical block to the first physical block in the assignment step.

6. A method for controlling access to one or more flash memories, in which data erasing is performed in physical blocks, comprising:

a logical block management step of forming plural logical blocks each composed of plural logical sectors to each of which a logical address for a host system is assigned;

a virtual block management step of forming plural virtual blocks into which physical blocks are divided;

a program-erase cycles management step of managing the number of program-erase cycles of each virtual block;

a first search step of searching out a first virtual block and a second virtual block, which first virtual block is a free virtual block of which the number of program-erase cycles is the smallest among free virtual blocks, which second virtual block is a free virtual block of which a number of program-erase cycles is the largest among free virtual blocks;

a assignment step of assigning a logical block to a virtual block which logical block is composed of plural logical sectors to each of which a logical address for a host system is assigned;

a second search step of searching out a third virtual block to which a logical block is assigned earliest among virtual blocks to each of which a logical block is assigned;

a data writing step of, in response to a request issued by the host system, identifying a logical block including a logical sector corresponding to a logical address pertaining to the request and stores data provided from the host system in a virtual block corresponding to the logical block identified;

a determination step of making a determination whether or not the number of program-erase cycles of the first virtual block is larger by a predetermined value or more than the number of program-erase cycles of the third virtual block; and

a data transfer step of performing data transfer for transferring data stored in the third virtual block to the second virtual block;

wherein, when assigning a logical block to a virtual block in the assignment step, making the determination in the determination step; and

wherein, in a case where the determination is positive, assigning the logical block to the third virtual block, in the assignment step, after completing the data transfer,

wherein, in a case where the determination is negative, assigning the logical block to the first physical block in the assignment step.