MEMORY DEVICE AND WEAR LEVELING METHOD THEREOF

• US 20100205363A1
• Filed: 12/29/2009
• Published: 08/12/2010
• Est. Priority Date: 02/10/2009
• Status: Abandoned Application

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Lee, Jamee Kim, HWANG, Joo-young, Kim, Hong-kug
• Application Number:
  US12/648,450
• Publication Number:
  US 20100205363A1
• Time in Patent Office: Days
• US Class Current: 711/104
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
• CPC Class Codes: G11C 16/3495 Circuits or methods to detect or delay wearout of nonvolatile EPROM or EEPROM memory devices, e.g. by counting numbers of erase or reprogram cycles, by using multiple memory areas serially or cyclically
• CPC Class Codes: G11C 29/88 with partially good memories
• CPC Class Codes: G11C 29/883 using a single defective memory device with reduced capacity, e.g. half capacity

Abstract

Disclosed is a memory device including a NVRAM and a page table, and a wear leveling method therefor. The page table includes mapping information which maps virtual addresses of the NVRAM with physical addresses of the NVRAM. A page table entry includes aging information which indicates the wear of a corresponding page. The aging information may be a remaining number of write operations allowed to the page. Whenever data is written in a page, a value indicating a remaining number of write operations allowed to that page is decremented.

Claims

1. A memory device comprising:

a memory including a non-volatile random access memory (NVRAM); and

a controller to control the memory,

wherein the controller manages a page table including mapping information that maps virtual addresses of the NVRAM to physical addresses of the NVRAM, and an entry of the page table includes aging information indicating the wear of a corresponding page of the NVRAM.

2. The memory device of claim 1, wherein the aging information indicates a remaining number of write operations allowed to the corresponding page, and whenever data is written on the corresponding page, the controller decrements by 1 the remaining number of write operations allowed to that page.

3. The memory device of claim 1, further comprising a non-volatile memory that is controlled by the controller,

wherein the controller stores aging information of each page in the non-volatile memory when power is off, restores a remaining number of write operations for each page stored in the non-volatile memory upon booting, and performs memory allocation on the memory based on the aging information of each page.

4. The memory device of claim 3, wherein the controller registers and manages a black list including information of one or more worn pages which are pages that are not to be used, stores the black list in the non-volatile memory when power is off, and restores the black list stored in the non-volatile memory upon booting.

5. The memory device of claim 1, wherein if a write operation is performed on a page where the number of write operations already performed on the page equals or exceeds a threshold value, the controller generates a page fault, copies content of the page to a free page, and modifies the page table corresponding to the page so that a virtual address of the page is mapped to a physical address of the free page.

6. The memory device of claim 1, wherein if a write operation is performed on a page where the number of write operations performed on the page equals or exceeds a threshold value, the controller generates a page fault and prevents memory allocation from being performed on the page.

7. The memory device of claim 6, wherein the controller performs memory allocation according to a buddy allocation algorithm based on a binary tree data structure, and if a page fault occurs at a node on the binary tree data structure during memory allocation, the controller marks the node and at least one upper node of the node.

8. The memory device of claim 7, wherein if page allocation is requested based on a size of at least one node and successive spaces have to be allocated, the controller prevents pages corresponding to the marked nodes from being allocated.

9. The memory device of claim 1, wherein the page table includes a layer-1 page table which manages physical addresses corresponding to virtual addresses in units of super sections that are larger than units of pages, and a layer-2 page table which manages physical addresses corresponding to virtual addresses in units of pages.

10. The memory device of claim 9, wherein the layer-1 page table includes information about a remaining number of write operations allowed to each supersection, and the layer-2 page table includes information about a remaining number of write operations allowed to each page.

11. The memory device of claim 1, wherein the page table includes a layer-2 page table that maps virtual addresses with physical addresses in units of pages, and a layer-1 page table that indicates a location of the layer-2 page table, wherein the layer-2 page table includes information about a remaining number of write operations allowed to each page.

12. The memory device of claim 1, wherein the entry of the page table includes identifier information indicating whether the page table includes pointer information indicating a location of a memory at which the aging information is stored.

13. The memory device of claim 12, wherein if a page is shared by two or more processes, the entry of the page table includes pointer information indicating a location of a memory storing aging information of the shared page, and if a page is used only by one process, the entry of the page table includes aging information of the page used by one process.

14. The memory device of claim 13, wherein when a page shared by two or more processes ceases to be shared, aging information corresponding to that page stored in a memory is copied to an aging field of that page.

15. The memory device of claim 12, wherein if a page which was previously not shared becomes shared by two or more processes, a value of an aging field of that page is copied to a location of a memory, and pointer information indicating the location is stored in the aging field of that page.

16. A method for wear leveling of a memory device, the memory device comprising a memory including a non-volatile random access memory (NVRAM) and a controller to control the memory, wherein a page table corresponding to the NVRAM includes mapping information which maps virtual addresses of the NVRAM with physical addresses of the NVRAM, and an entry of the page table include aging information which indicates the wear of a corresponding page, the method comprising:

to writing data on a page; and

decrementing a remaining number of write operations by one in response to the writing on the page, the remaining number of write operations being indicated in aging information provided in an entry of the page table corresponding to the page.

17. The method of claim 16, further comprising:

storing aging information of each page in a non-volatile memory when power is off;

restoring a remaining number of write operations for each page stored in the non-volatile memory upon booting; and

performing memory allocation based on the restored remaining number of write operations.

18. The method of claim 16, further comprising registering a worn page whose remaining number of write operations has reached a threshold value, in a black list, and managing the black list.

19. The method of claim 16, wherein when the number of write operations performed on the page exceeds a threshold value, the method further comprises:

generating a page fault;

copying content of the page to a free page; and

modifying the page table so that a virtual address of the page is mapped to a physical address of the free page.

20. The method of claim 16, further comprising performing memory allocation based on the aging information, wherein the performing of the memory allocation comprises generating a page fault if a write operation is performed on the page where the number of write operations allowed on the page has reached a threshold value, and preventing the page from being allocated.

21. The method of claim 20, wherein:

the performing of the memory allocation comprises performing memory allocation according to a buddy algorithm that performs page allocation based on a binary tree data structure, and

if a page fault is generated at a node on the binary tree data structure when the memory allocation is performed, the method further comprises;

marking the node and at least one upper node of the node; and

determining whether page allocation based on a size of the at least one upper node is requested and whether allocation of successive spaces is requested,

wherein if the page allocation based on the size of the at least one upper node is requested and the allocation of successive spaces is requested, pages corresponding to the marked nodes are excluded from the memory allocation.

22. The method of claim 16, wherein the page table includes identifier information indicating whether the entry of the page table includes pointer information indicating a location of a memory at which the aging information is stored, or whether the entry of the page table includes the aging information.

23. The method of claim 22, wherein if the page is shared by two or more processes, the entry of the page table includes the pointer information indicating the location of the memory to storing the aging information of the shared page, and if the page is used by one process, the entry of the page table includes the aging information of the page.