System and Method for Managing Memory in a Multiprocessor Computing Environment

• US 20100205381A1
• Filed: 02/06/2009
• Published: 08/12/2010
• Est. Priority Date: 02/06/2009
• Status: Abandoned Application

• Current Assignee: Breakingpoint Systems Incorporated (Keysight Technologies, Inc.)
• Original Assignee: Breakingpoint Systems Incorporated (Keysight Technologies, Inc.)
• Inventors: Canion, Rodney S.
• Application Number:
  US12/367,138
• Publication Number:
  US 20100205381A1
• Time in Patent Office: Days
• US Class Current: 711/147
• CPC Class Codes: G06F 9/5016 the resource being the memory

Abstract

A method for managing a memory communicatively coupled to a plurality of processors may include analyzing a data structure associated with a processor to determine if one or more portions of memory associated with the processor are sufficient to store data associated with an operation of the processor. The method may also include storing data associated with the operation in the one or more portions of the memory associated with the processor if the portions of memory associated with the processor are sufficient. If the portions of memory associated with the processor are not sufficient, the method may include determining if at least one portion of the memory is unassociated with any of the plurality of processors storing data associated with the operation in the at least one unassociated portion of the memory.

Claims

1. A system comprising:

a plurality of processors; and

a memory communicatively coupled to each of the plurality of processors, the memory having a plurality of portions, and each portion having a marker indicative of whether such portion is associated with one of the plurality of processors;

wherein at least one of the plurality of processors is configured to maintain an associated data structure, the data structure indicative of the portions of the memory associated with the processor.

2. A system according to claim 1, wherein each marker is further indicative of one of the plurality of processors associated with the portion of memory.

3. A system according to claim 1, wherein at least one of the plurality of processors is configured to:

analyze its associated data structure to determine if the portions of memory associated with the processor are sufficient to store data associated with an operation of the processor;

store data associated with the operation in the portions of the memory associated with the processor if the portions of memory associated with the processor are sufficient; and

if the portions of memory associated with the processor are not sufficient;

determine if at least one portion of the memory is unassociated with any of the plurality of processors; and

store data associated with the operation in the at least one unassociated portion of the memory.

4. A system according to claim 3, wherein the at least one processor is configured to, if the portions of memory associated with the processor are not sufficient, modify the marker of the at least one unassociated portion of the memory to indicate that the at least one unassociated portion of the memory is associated with the at least one processor.

5. A system according to claim 3, wherein the at least one processor is configured to, if the portions of memory associated with the processor are not sufficient, modify its associated data structure to indicate that the at least one processor is associated with the at least one unassociated portion of the memory.

6. A system according to claim 3, wherein the at least one processor is configured to determine if the at least one portion of the memory is unassociated with any of the plurality of processors by analyzing the plurality of markers.

7. A system according to claim 1, wherein the plurality of processors includes at least one of a thread, a core, or a monolithic processor.

8. A system according to claim 1, wherein the plurality processors includes at least one of a general purpose processor and a network processor.

9. A method for managing a memory communicatively coupled to a plurality of processors, comprising:

analyzing a data structure associated with a processor to determine if one or more portions of memory associated with the processor are sufficient to store data associated with an operation of the processor;

storing data associated with the operation in the one or more portions of the memory associated with the processor if the portions of memory associated with the processor are sufficient; and

if the portions of memory associated with the processor are not sufficient;

determining if at least one portion of the memory is unassociated with any of the plurality of processors; and

storing data associated with the operation in the at least one unassociated portion of the memory.

10. A method according to claim 9, further comprising modifying a marker associated with the at least one unassociated portion of the memory to indicate that the at least one unassociated portion of the memory is associated with the processor if the one or more portions of memory associated with the processor are not sufficient.

11. A method according to claim 9, further comprising modifying the data structure associated with the processor to indicate that the processor is associated with the at least one unassociated portion of the memory.

12. A method according to claim 9, further comprising analyzing a plurality of markers, each marker associated with a portion of the memory and indicative of whether such portion is associated with one of the plurality of processors, to determine if the at least one portion of the memory is unassociated with any of the plurality of processors.

13. A method according to claim 9, wherein the processor includes at least one of a thread, a core, or a monolithic processor.

14. A method according to claim 9, wherein the plurality processors includes at least one of a general purpose processor and a network processor.

15. A network processor, configured to be communicatively coupled to at least one other network processor and a memory, and further configured to:

analyze a data structure associated with the network processor to determine if one or more portions of memory associated with the network processor are sufficient to store data associated with an operation of the network processor;

store data associated with the operation in the one or more portions of the memory associated with the network processor if the portions of memory associated with the network processor are sufficient; and

if the portions of memory associated with the network processor are not sufficient;

determine if at least one portion of the memory is unassociated with any of the at least one other network processor; and

store data associated with the operation in the at least one unassociated portion of the memory.

16. A network processor according to claim 15, the network processor further configured to modify a marker associated with the at least one unassociated portion of the memory to indicate that the at least one unassociated portion of the memory is associated with the processor if the one or more portions of memory associated with the processor are not sufficient.

17. A network processor according to claim 15, further comprising modifying the data structure associated with the processor to indicate that the network processor is associated with the at least one unassociated portion of the memory.

18. A network processor according to claim 15, further comprising analyzing a plurality of markers, each marker associated with a portion of the memory and indicative of whether such portion is associated with the network processor or the at least one other processor, to determine if the at least one portion of the memory is unassociated with the at least one other network processor.

19. A network processor according to claim 15, wherein the network processor includes at least one of a network processor thread, a core of a multicore network processor, or a monolithic network processor.

20. A network processor according to claim 15, wherein one or more portions of memory each include a buffer pool.