TRANSLATED MEMORY PROTECTION

• US 20100205413A1
• Filed: 04/16/2010
• Published: 08/12/2010
• Est. Priority Date: 08/22/1996
• Status: Active Grant

• Current Assignee: Liberty Patents LLC
• Original Assignee: Edmund J. Kelly, Malcolm J. Wing, Robert F. Cmelik
• Inventors: Wing, Malcolm J., Cmelik, Robert F., Kelly, Edmund J.
• Granted Patent: US 8,495,337 B2
• Time in Patent Office: Days
• US Class Current: 712/226
• CPC Class Codes: G06F 13/4239 with asynchronous protocol
• CPC Class Codes: G06F 9/3808 for instruction reuse, e.g. trace cache, branch target cache
• CPC Class Codes: G06F 9/3812 with instruction modification, e.g. store into instruction stream
• CPC Class Codes: G06F 9/45504 Abstract machines for programme code execution, e.g. Java virtual machine [JVM], interpreters, emulators

Abstract

A method of responding to an attempt to write a memory address including a target instruction which has been translated to a host instruction for execution by a host processor including the steps of marking a memory address including a target instruction which has been translated to a host instruction, detecting a memory address which has been marked when an attempt is made to write to the memory address, and responding to the detection of a memory address which has been marked by protecting a target instruction at the memory address until it has been assured that translations associated with the memory address will not be utilized before being updated.

Claims

1. A host computer system comprising:

a first primitive operation generated from a first target instruction in a target program;

a second primitive operation generated from a second target instruction in said target program;

a translator configured to schedule said first primitive operation and said second primitive operation into an instruction of said host computer system; and

said translator also configured to provide an indication that said first and second target instructions have been translated into said first and second primitive operations.

2. The host computer system of claim 1 wherein said translator is also for providing an indication that said first and second target instructions have been translated into said first and second primitive operations.

3. The host computer system of claim 1, wherein said first target instruction is compliant with an x-86 instruction set.

4. The host computer system of claim 1 further comprising a plurality of host processor registers configured for processing said first primitive operation and a first plurality of target registers configured to hold an official state of a target processor, wherein said target processor is capable of natively executing said first instruction.

5. The host computer system of claim 4 further comprising a second plurality of target registers configured to hold a temporary state of said target processor.

6. The host computer system of claim 5 comprising circuitry configured to transfer, via hardware operations, the contents of said second plurality of target registers to said first plurality of target registers.

7. The host computer system of claim 1, wherein said second primitive operation is a speculative operation.

8. A method comprising:

generating a first primitive operation from a first target instruction in a target program;

generating a second primitive operation from a second target instruction in said target program;

scheduling said first primitive operation and said second primitive operation into a host instruction of a host computer system; and

executing said host instruction on a host computer system, wherein said host computer is incapable of natively executing said first target instruction.

9. The method of claim 8 further comprising providing an indication that said first and second target instructions have been translated into said first and second primitive operations.

10. The method of claim 8 wherein said first target instruction is compliant with an x-86 instruction set.

11. The method of claim 8 further comprising transferring the contents of a first plurality of target registers configured to hold an official state of a target processor to a second plurality of target registers configured to hold a temporary state of said target processor, wherein said target processor is capable of natively executing said first instruction.

12. The method of claim 8 wherein said second primitive operation is a speculative operation.

13. A host computer system comprising:

means for generating a first primitive operation from a first target instruction in a target program;

means for generating a second primitive operation from a second target instruction in said target program;

means for scheduling said first primitive operation and said second primitive operation into a host instruction of a host computer system; and

means for executing said host instruction on a host computer system, wherein said host computer is incapable of natively executing said first target instruction.

14. The host computer system of claim 13 further comprising means for providing an indication that said first and second target instructions have been translated into said first and second primitive operations.

15. The host computer of claim 13 wherein said first target instruction is compliant with an x-86 instruction set.

16. The host computer of claim 13 wherein said second primitive operation is a speculative operation.

17. An article of manufacture including a computer readable medium having instructions stored thereon that, responsive to execution by a computing device, cause the computing device to perform operations comprising:

generating a first primitive operation from a first target instruction in a target program;

generating a second primitive operation from a second target instruction in said target program;

scheduling said first primitive operation and said second primitive operation into a host instruction of a host computer system; and

executing said host instruction on a host computer system, wherein said host computer is incapable of natively executing said first target instruction.

18. The article of manufacture of claim 17 wherein said operations further comprise providing an indication that said first and second target instructions have been translated into said first and second primitive operations.

19. The article of manufacture of claim 17 wherein said first target instruction is compliant with an x-86 instruction set.

20. The article of manufacture of claim 17 wherein said second primitive operation is a speculative operation.