PIPELINED MICROPROCESSOR WITH FAST CONDITIONAL BRANCH INSTRUCTIONS BASED ON STATIC SERIALIZING INSTRUCTION STATE

• US 20100205415A1
• Filed: 06/09/2009
• Published: 08/12/2010
• Est. Priority Date: 02/12/2009
• Status: Active Grant

• Current Assignee: VIA Technologies Incorporated (VIA Technologies)
• Original Assignee: VIA Technologies Incorporated (VIA Technologies)
• Inventors: Parks, Terry, Bean, Brent, Henry, G. Glenn
• Granted Patent: US 8,131,984 B2
• Time in Patent Office: Days
• US Class Current: 712/234
• CPC Class Codes: G06F 9/30058 Conditional branch instructions
• CPC Class Codes: G06F 9/3867 using instruction pipelines

Abstract

A microprocessor includes a control register that stores a control value that affects operation of the microprocessor. An instruction set architecture includes a conditional branch instruction that specifies a branch condition based on the control value stored in the control register, and a serializing instruction that updates the control value in the control register. The microprocessor completes all modifications to flags, registers, and memory by instructions previous to the serializing instruction and to drain all buffered writes to memory before it fetches and executes the next instruction after the serializing instruction. Execution units update the control value in the control register in response to the serializing instruction. A fetch unit fetches, decodes, and unconditionally correctly resolves and retires the conditional branch instruction based on the control value stored in the control register rather than dispatching the conditional branch instruction to the execution units to be resolved.

Claims

1. A pipelined microprocessor, comprising:

a control register, configured to store a control value that affects operation of the microprocessor;

an instruction set architecture, that includes a conditional branch instruction that specifies a branch condition based on the control value stored in the control register, wherein the instruction set architecture further includes a serializing instruction that updates the control value in the control register, wherein the microprocessor is configured to complete all modifications to flags, registers, and memory by instructions previous to the serializing instruction and to drain all buffered writes to memory before it fetches and executes the next instruction after the serializing instruction;

execution units, coupled to the control register, configured to update the control value in the control register in response to the serializing instruction; and

a fetch unit, coupled to the control register, configured to fetch, decode, and unconditionally correctly resolve and retire the conditional branch instruction based on the control value stored in the control register rather than dispatching the conditional branch instruction to the execution units to be resolved.

2. The pipelined microprocessor of claim 1, further comprising:

a general purpose register, coupled to the execution units, configured to store a second value;

wherein the instruction set architecture further includes a second conditional branch instruction that specifies a second branch condition based on the second value stored in the general purpose register;

wherein the fetch unit is further configured to fetch and decode the second conditional branch instruction based on the second value stored in the general purpose register and to dispatch the second conditional branch instruction to the execution units to be resolved.

3. The pipelined microprocessor of claim 1, wherein the conditional branch instruction instructs the microprocessor to unconditionally correctly resolve and retire the conditional branch instruction based on the control value stored in the control register without regard to whether the execution units have updated the control value in the control register in response to the serializing instruction.

4. The pipelined microprocessor of claim 1, wherein the microprocessor is further configured to implement the serializing instruction in a microcode routine executed by the microprocessor, wherein the microcode routine includes a flushing instruction that follows an updating instruction in the microcode routine program order, wherein the updating instruction updates the control value in the control register with the value specified by the serializing instruction, wherein the flushing instruction flushes the microprocessor pipeline of all instructions after the flushing instruction in the microcode routine program order.

5. The pipelined microprocessor of claim 1, wherein the conditional branch instruction is included within a user program stored in a system memory coupled to the microprocessor.

6. The pipelined microprocessor of claim 1, wherein the conditional branch instruction is included within a microcode routine stored in a microcode memory of the microprocessor.

7. The pipelined microprocessor of claim 1, wherein the control register value controls whether or not the microprocessor operates in a mode that employs memory protection facilities of the microprocessor.

8. The pipelined microprocessor of claim 1, wherein the control register value controls whether or not the microprocessor operates in a memory paging mode.

9. The pipelined microprocessor of claim 1, wherein the control register value controls whether or not the microprocessor automatically performs alignment checking of memory references.

10. The pipelined microprocessor of claim 1, wherein the control register value controls whether virtual mode extensions of the microprocessor are enabled.

11. The pipelined microprocessor of claim 1, wherein the control register comprises a model specific register (MSR).

12. The pipelined microprocessor of claim 1, wherein the control register comprises a descriptor table register of the microprocessor.

13. The pipelined microprocessor of claim 1, wherein the control register comprises a task register of the microprocessor.

14. The pipelined microprocessor of claim 1, wherein the serializing instruction invalidates a cache memory of the microprocessor.

15. The pipelined microprocessor of claim 1, wherein the serializing instruction invalidates an entry of a translation lookaside buffer of the microprocessor.

16. The pipelined microprocessor of claim 1, wherein the serializing instruction resumes the microprocessor from system management mode (SMM).

17. A method for fast execution of a conditional branch instruction in a pipelined microprocessor having a control register that stores a control value that affects operation of the microprocessor, the microprocessor also having instruction set architecture that includes a serializing instruction that updates the control value in the control register, wherein the microprocessor is configured to complete all modifications to flags, registers, and memory by instructions previous to the serializing instruction and to drain all buffered writes to memory before it fetches and executes the next instruction after the serializing instruction, the method comprising:

including in the instruction set architecture a conditional branch instruction that specifies a branch condition based on the control value stored in the control register;

updating the control value in the control register in response to the serializing instruction, wherein said updating the control value in the control register is performed by execution units of the microprocessor; and

fetching, decoding, and unconditionally correctly resolving and retiring the conditional branch instruction based on the control value stored in the control register rather than dispatching the conditional branch instruction to the execution units to be resolved, wherein said fetching, decoding, and unconditionally correctly resolving and retiring are performed by a fetch unit of the microprocessor.

18. The method of claim 17, further comprising:

having in the instruction set architecture a second conditional branch instruction that specifies a second branch condition based on a second value stored in a general purpose register of the microprocessor;

fetching and decoding the second conditional branch instruction based on the second value stored in the general purpose register; and

dispatching the second conditional branch instruction to the execution units to be resolved, wherein said fetching and decoding and dispatching the second conditional branch instruction are performed by the fetch unit.

19. The method of claim 17, wherein the conditional branch instruction instructs the microprocessor to unconditionally correctly resolve and retire the conditional branch instruction based on the control value stored in the control register without regard to whether the execution units have updated the control value in the control register in response to the serializing instruction.

20. The method of claim 17, wherein the microprocessor is further configured to implement the serializing instruction in a microcode routine executed by the microprocessor, wherein the microcode routine includes a flushing instruction that follows an updating instruction in the microcode routine program order, wherein the updating instruction updates the control value in the control register with the value specified by the serializing instruction, wherein the flushing instruction flushes the microprocessor pipeline of all instructions after the flushing instruction in the microcode routine program order.

21. The method of claim 17, wherein the conditional branch instruction is included within a user program stored in a system memory coupled to the microprocessor.

22. The method of claim 17, wherein the conditional branch instruction is included within a microcode routine stored in a microcode memory of the microprocessor.

23. The method of claim 17, wherein the control register value controls whether or not the microprocessor operates in a mode that employs memory protection facilities of the microprocessor.

24. The method of claim 17, wherein the control register value controls whether or not the microprocessor operates in a memory paging mode.

25. The method of claim 17, wherein the control register value controls whether or not the microprocessor automatically performs alignment checking of memory references.

26. The method of claim 17, wherein the control register value controls whether virtual mode extensions of the microprocessor are enabled.

27. The method of claim 17, wherein the control register comprises a model specific register (MSR).

28. The method of claim 17, wherein the control register comprises a descriptor table register of the microprocessor.

29. The method of claim 17, wherein the control register comprises a task register of the microprocessor.

30. The method of claim 17, wherein the serializing instruction invalidates a cache memory of the microprocessor.

31. The method of claim 17, wherein the serializing instruction invalidates an entry of a translation lookaside buffer of the microprocessor.

32. The method of claim 17, wherein the serializing instruction resumes the microprocessor from system management mode (SMM).

33. A computer program product for use with a computing device, the computer program product comprising:

a computer usable storage medium, having computer readable program code embodied in said medium, for specifying a pipelined microprocessor, the computer readable program code comprising;

first program code for specifying a control register, configured to store a control value that affects operation of the microprocessor;

second program code for specifying an instruction set architecture, that includes a conditional branch instruction that specifies a branch condition based on the control value stored in the control register, wherein the instruction set architecture further includes a serializing instruction that updates the control value in the control register, wherein the microprocessor is configured to complete all modifications to flags, registers, and memory by instructions previous to the serializing instruction and to drain all buffered writes to memory before it fetches and executes the next instruction after the serializing instruction;

third program code for specifying execution units, coupled to the control register, configured to update the control value in the control register in response to the serializing instruction; and

fourth program code for specifying a fetch unit, coupled to the control register, configured to fetch, decode, and unconditionally correctly resolve and retire the conditional branch instruction based on the control value stored in the control register rather than dispatching the conditional branch instruction to the execution units to be resolved.