Systems and Methods for Modular Power Management

• US 20100205462A1
• Filed: 07/18/2006
• Published: 08/12/2010
• Est. Priority Date: 07/18/2006
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Agere Systems Incorporated (Broadcom, Inc.)
• Inventors: Sakai, Tatsuya, Rauschmayer, Richard, Strauss, Steven E.
• Granted Patent: US 8,291,251 B2
• Time in Patent Office: Days
• US Class Current: 713/300
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3237 by disabling clock generation or distribution
• CPC Class Codes: G06F 1/3268 Power saving in hard disk drive
• CPC Class Codes: G06F 1/3287 by switching off individual functional units in the computer system
• CPC Class Codes: G11B 19/00 Driving, starting, stopping record carriers not specifically of filamentary or web form, or of supports therefor; Control thereof; Control of operating function ; Driving both disc and head
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A modular, adaptive power management system includes a hard disk drive controller, a read channel module, a host interface controller and a power manager system. The hard disk controller includes a processor executing firmware, and the host interface controller provides for host access via a host interface. The system includes a power island register and an oscillation control register. Both registers are writable via the firmware and via the host interface. The hard disk controller, the interface controller, the read channel module and the power manager system are implemented across two or more distinct power islands and use two or more distinct clocks. Power to the two or more distinct power islands is at least in part controlled by the power manager system via the power island register, and the two or more distinct clocks are each controlled by the power manager system via the oscillation control register.

Claims

1. A modular, adaptive power management system, the power management system comprising:

a power island controller;

an oscillation controller; and

wherein the oscillation controller and the power island controller are implemented in a modular power management circuit.

2. The power management system of claim 1, wherein the power management system further includes a processor, and wherein the processor includes firmware executable to operate the power management system.

3. The power management system of claim 2, wherein the power management system is deployed in relation to a device, wherein the device includes a first power island and a second power island, and wherein the power island controller includes a first register bit writable by the firmware and operable to disable power to the first power island and a second register bit writable by the firmware and operable to disable power to the second power island.

4. The power management system of claim 3, wherein the firmware is operable to implement an adaptive power management scheme.

5. The power management system of claim 3, wherein the power management system further includes a translator interface, and wherein the first register bit and the second register bit are writable via the translator interface.

6. The power management system of claim 5, wherein a host is operable to implement a coarse power management scheme, wherein the power management system is accessible to the host via the translator interface, and wherein the firmware is operable to implement a finer adaptive power management scheme.

7. The power management system of claim 2, wherein the power management system is deployed in relation to a device, wherein the device includes a first circuit portion and a second circuit portion, and wherein the oscillation controller a first register bit writable by the firmware and operable to disable a first clock to the first circuit portion and a second register bit writable by the firmware and operable to disable a second clock to the second power island.

8. The power management system of claim 2, wherein the power management system is deployed in relation to a device, wherein the device includes a first circuit portion and a second circuit portion, and wherein the oscillation controller a register bit writable by the firmware and operable to disable both a first clock to the first circuit portion and a second clock to the second power island.

9. The power management system of claim 8, wherein the register bit is further operable to disable an oscillator from which the first clock and the second clock are derived.

10. The power management system of claim 1, wherein the power management system further includes a translator interface, wherein the translator interface is operable to at least in part control operation of the power island controller and the oscillation controller.

11. The power management system of claim 10, wherein the translator interface is selected from a group consisting of:

an ATA interface, a SATA interface, an MMC interface, CE-ATA interface, and an SDIO interface.

12. The power management system of claim 10, wherein the power management system further includes a processor, and wherein the processor includes firmware executable to operate the power management system.

13. The power management system of claim 1, wherein the power management system is register based, and wherein the power management system is deployable in relation to a variety of host systems.

14. The power management system of claim 13, wherein one of the variety of host systems is a hard disk drive system.

15. A reusable, modular power management circuit for use in a variety of systems, the power management circuit comprising:

a power island control register, wherein the power island control register is associated with a plurality of power island control bits, and wherein each of the plurality of power island control bits is operable to disable power to a given power island;

an oscillation control register, wherein the oscillation control register is associated with a plurality of oscillation control bits, and wherein each of the plurality of oscillation control bits is operable to disable a given clock; and

a translator interface, wherein the translator interface is operable to receive a standard power management command and to translate the standard power management command into a write to the power island control register and the oscillation control register, and wherein the write to the power island control register and the oscillation control register implements a tailored power management scheme related to the standard power management command.

16. The power management circuit of claim 15, the circuit further comprising:

an embedded processor executing firmware, wherein the embedded processor at least in part controls operation of the translator interface.

17. The power management circuit of claim 16, wherein the firmware is upgradeable.

18. The power management circuit of claim 15, wherein a first of the plurality of oscillation control bits is operable to disable an oscillator, wherein a second of the oscillation control bits is operable to gate all clocks derived from the oscillator, and wherein a third of the oscillation control bits is operable to gate less than all clocks derived from the oscillator.

19. The power management circuit of claim 15, wherein the standard command is selected from a group consisting of:

an ATA command and an SATA command.

20. A hard disk drive system, wherein the hard disk drive system includes:

a hard disk controller;

an interface controller;

a read channel module;

a power manager system; and

wherein the hard disk controller, the interface controller, the read channel module and the power manager system are implemented across two or more distinct power islands, and wherein power to the two or more distinct power islands is at least in part controlled by the power manager system.

21. The hard disk drive system of claim 20, wherein the hard disk controller, the interface controller, the read channel module and the power manager system utilize two or more distinct clocks, and wherein the two or more distinct clocks are each controlled by the power manager system.

22. The hard disk drive system of claim 20, wherein the interface controller is operable to provide a translator interface selected from a group consisting of:

an ATA interface, an SATA interface, an MMC interface, a CE-ATA interface, and an SDIO interface.

23. The hard disk drive system of claim 20, wherein the hard disk drive system further includes:

a processor executing firmware, wherein the firmware is operable to implement an adaptive power management scheme via the power manager system.

24. The hard disk drive system of claim 23, wherein the interface controller is operable to provide a translator interface, wherein the translator interface is operable to receive a host command that causes a selected power mode to be implemented via the power manager system.