FLASH BACKED DRAM MODULE WITH STATE OF HEALTH AND/OR STATUS INFORMATION ACCESSIBLE THROUGH A CONFIGURATION DATA BUS

• US 20100205470A1
• Filed: 02/11/2009
• Published: 08/12/2010
• Est. Priority Date: 02/11/2009
• Status: Active Grant

• Current Assignee: Sandisk Technologies Incorporated (Western Digital Corporation)
• Original Assignee: STEC Incorporated (Western Digital Corporation)
• Inventors: MOSHAYEDI, Mark, Finke, Douglas
• Granted Patent: US 8,566,639 B2
• Time in Patent Office: Days
• US Class Current: 713/340
• CPC Class Codes: G11C 2029/4402 Internal storage of test result, quality data, chip identification, repair information
• CPC Class Codes: G11C 5/141 Battery and back-up supplies
• CPC Class Codes: G11C 5/143 Detection of memory cassette insertion or removal; Continuity checks of supply or ground lines; Detection of supply variations, interruptions or levels G11C5/148 takes precedence; Switching between alternative supplies G11C5/141 takes precedence
• CPC Class Codes: G11C 7/24 Memory cell safety or protection circuits, e.g. arrangements for preventing inadvertent reading or writing; Status cells; Test cells

Abstract

A memory device includes: volatile memory; an interface for connecting to a backup power source; non-volatile memory; a first configuration data bus for accessing parameters describing substantially permanent characteristics of the volatile memory; a second configuration data bus for accessing at least one of state of health information of the backup power source and status information of the memory device, wherein the first configuration data bus and the second configuration data bus implement a same bus protocol; a controller programmed to detect a loss of power of a primary power source and move data from the volatile memory to the non-volatile memory, wherein configuration information of the controller is at least one of readable and writable through the first configuration data bus; and wherein at least one of the state-of-health information and the status information is at least one of readable and writable through the second configuration data bus.

Claims

1. A memory device, comprising:

volatile memory;

an interface for connecting to a backup power source arranged to power the volatile memory upon a loss of power of a primary power source;

non-volatile memory;

a first configuration data bus for accessing parameters describing substantially permanent characteristics of the volatile memory;

a second configuration data bus for accessing at least one of state of health information of the backup power source and status information of the memory device, wherein the first configuration data bus and the second configuration data bus implement a same bus protocol;

a controller, in communication with the first configuration data bus, the second configuration data bus, the volatile memory, and the non-volatile memory, that is programmed to detect a loss of power of the primary power source and in response move data from the volatile memory to the non-volatile memory,

wherein first configuration information of the controller is at least one of readable and writable through the first configuration data bus; and

wherein at least one of the state of health information and the status information is at least one of readable and writable through the second configuration data bus.

2. The memory device of claim 1, wherein the state-of-health information includes a state of the power source indicating that the backup power source is at least one of charged, discharged, and charging.

3. The memory device of claim 1, wherein the state-of-health information indicates whether any capacitors comprising the backup power source have failed.

4. The memory device of claim 3, wherein the state-of-health information indicates which of the capacitors comprising the backup power source have failed.

5. The memory device of claim 1, wherein the state-of-health information indicates a type of backup power source.

6. The memory device of claim 5, wherein the type can be capacitor or battery.

7. The memory device of claim 1, wherein the status information indicates that the non-volatile memory is at least one of written, erased, erasing, and defective.

8. The memory device of claim 1, wherein the status information includes header information of the non-volatile memory.

9. The memory device of claim 1, wherein the status information includes at least one of a number of bad memory blocks, a number of spare memory blocks, a number of completed download cycles, a number of ECC errors in a last download, a number of ECC errors in a last restore, a status of a last download, and a status of a last restore.

10. The memory device of claim 1, wherein the volatile memory comprises a dynamic random access memory.

11. The memory device of claim 1, wherein the non-volatile memory comprises electrically erasable programmable read-only memories (EEPROMs).

12. The memory device of claim 1, wherein the controller comprises at least one of an application-specific integrated circuit (ASIC) and a field programmable gate array (FPGA).

13. The memory device of claim 1, wherein, the controller is further programmed to move data from the non-volatile memory to the volatile memory upon a restoration of power of the primary power source.

14. The memory device of claim 1, wherein the same bus protocol is a Inter-Integrated Circuit bus protocol.

15. The memory device of claim 1, wherein the first configuration data bus and second configuration data bus comprise one physical Inter-Integrated Circuit bus and wherein the first configuration data bus and second configuration data bus use different address ranges.

16. The memory device of claim 1, wherein the parameters comprise serial presence detect information.