FAST PHASE-FREQUENCY DETECTOR ARRANGEMENT

• US 20100205488A1
• Filed: 04/13/2010
• Published: 08/12/2010
• Est. Priority Date: 03/29/2004
• Status: Active Grant

• Current Assignee: III Holdings 6, LLC
• Original Assignee: NXP B.V. (NXP Semiconductors NV)
• Inventors: STIKVOORT, Eduard Ferdinand, SANDULEANU, Mihai Adrian Tiberiu
• Granted Patent: US 7,957,500 B2
• Time in Patent Office: Days
• US Class Current: 714/700
• CPC Class Codes: H03L 7/087 using at least two phase detectors or a frequency and phase detector in the loop
• CPC Class Codes: H03L 7/0896 the current generators being controlled by differential up-down pulses
• CPC Class Codes: H03L 7/0898 the source or sink current values being variable H03L7/0896 takes precedence

Abstract

The present invention relates to a detector arrangement and a charge pump circuit for a recovery circuit recovering timing information for random data. The detector arrangement comprises first latch means for sampling a quadrature component of a reference signal based on an input signal, to generate a first binary signal, a second latch means for sampling an in-phase component of the reference signal based on the input signal, to generate a second binary signal, and a third latch means for sampling the first binary signal based on the second binary signal, to generate a frequency error signal. Thus, a simple and fast detection circuitry can be achieved based on a digital implementation. Furthermore, the charge pump circuit comprises a differential input circuit and control means for controlling a tail current of the differential input circuit in response to a frequency-locked state of frequency detector arrangement. This provides the advantage that behavior of the charge pump circuit can alleviate extra ripple generated by the detector arrangement.

Claims

1. A detector arrangement for detecting a frequency error between an input signal and a reference signal, said detector arrangement comprising:

a) a first latch for sampling a quadrature component of said reference signal based on said input signal, to generate a first binary signal;

b) a second latch for sampling an in-phase component of said reference signal based on said input signal, to generate a second binary signal; and

c) a third latch for sampling said first binary signal based on said second binary signal, to generate a frequency error signal.

2. A detector arrangement according to claim 1, further comprising a controller for selectively suppressing operation of a charge pump circuit to which said first binary signal is supplied, in response to a control signal derived from said second binary signal.

3. A detector arrangement according to claim 1, wherein said first and second latches each comprise a double-edge triggered flip-flop arrangement.

4. A detector arrangement according to claim 3, wherein said double-edge triggered flip-flop arrangement comprises first and second D-latch circuits receiving said input signal and being respectively controlled by a direct version and an inversed version of the respective component of said reference signal, and a multiplexer circuit being controlled by said inversed version of said respective component.

5. A detector arrangement according to claim 1, wherein said third latch comprises a D-latch circuit receiving said first binary signal and being controlled by said second binary signal.

6. A detector arrangement according to claim 1, wherein said reference signal is a clock signal to be recovered from said input signal.

7. A detector arrangement according to claim 2, wherein said first and second binary signals are supplied to said charge pump circuit via at least one of respective amplifier and level shifter circuits.

8. A detector arrangement according to claim 7, wherein said amplifier circuits each comprise a combination of a feedback amplifier and a feedforward amplifier.

13. A recovery circuit for recovering timing information for random data, said recovery circuit comprising a detector arrangement according to any claim 1, wherein said frequency error signal generated by said detector arrangement is supplied to said charge pump circuit, and wherein said frequency-locked state is signaled by using said second binary signal generated by said detector arrangement.

9-12. -12. (canceled)

14. A method of detecting a frequency error between an input signal and a reference signal, said method comprising the steps of:

a) sampling a quadrature component of said reference signal based on said input signal, to generate a first binary signal;

b) sampling an in-phase component of said reference signal based on said input signal, to generate a second binary signal; and

c) sampling said first binary signal based on said second binary signal, to generate a frequency error signal.

15. (canceled)