Semiconductor device and method of manufacturing semiconductor device

• US 20100207093A1
• Filed: 02/16/2010
• Published: 08/19/2010
• Est. Priority Date: 02/17/2009
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: NEC Electronics Corporation (Renesas Electronics Corporation)
• Inventors: Kaneko, Kishou, Hayashi, Yoshihiro, Inoue, Naoya
• Granted Patent: US 8,390,124 B2
• Time in Patent Office: Days
• US Class Current: 257/4
• CPC Class Codes: H01L 21/76807 for dual damascene structures
• CPC Class Codes: H10N 70/028 by conversion of electrode material, e.g. oxidation
• CPC Class Codes: H10N 70/20 Multistable switching devices, e.g. memristors
• CPC Class Codes: H10N 70/826 adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
• CPC Class Codes: H10N 70/8833 Binary metal oxides, e.g. TaOx

Abstract

Provided is a semiconductor device including a substrate, and a first wiring layer, a second wiring layer, and a switch via formed on the substrate. The first wiring layer has first wiring formed therein and the second wiring layer has second wiring formed therein. The switch via connects the first wiring and the second wiring. The switch via includes at least at its bottom a switch element including a resistance change layer. A resistance value of the resistance change layer changes according to a history of an electric field applied thereto.

Claims

1. A semiconductor device comprising:

a substrate;

a first wiring layer formed on the substrate;

first wiring formed in the first wiring layer;

a second wiring layer located above the first wiring layer;

second wiring formed in the second wiring layer; and

a switch via for connecting the first wiring and the second wiring,

the switch via comprising at least at a bottom thereof a switch element, the switch element including a resistance change layer having a resistance value that changes according to a history of an electric field applied thereto.

2. A semiconductor device according to claim 1, further comprising a wiring via for connecting the first wiring and the second wiring, the wiring via being formed in a layer in which the switch via is formed, the wiring via not including the switch element.

3. A semiconductor device according to claim 1, wherein the switch via is formed of metal except for the switch element.

4. A semiconductor device according to claim 3, wherein the switch element includes an upper electrode layer located between the metal forming the switch via and the resistance change layer.

5. A semiconductor device according to claim 4, wherein the resistance change layer and the upper electrode layer are formed at the bottom and on a side of the switch via.

6. A semiconductor device according to claim 4, wherein the upper electrode layer includes one of a single layer film formed of one selected from a first group consisting of Ta, Ti, W, Ru, Pt, Ir, a nitride of Ta, a nitride of Ti, a nitride of W, a nitride of Ru, a nitride of Pt, and a nitride of Ir, and a laminated film in which two or more selected from the first group are laminated.

7. A semiconductor device according to claim 1, wherein the resistance change layer is directly connected to the first wiring.

8. A semiconductor device according to claim 1, wherein the switch element includes a lower electrode layer located between the first wiring and the resistance change layer.

9. A semiconductor device according to claim 8, wherein the resistance change layer and the lower electrode layer are formed at the bottom and on a side of the switch via.

10. A semiconductor device according to claim 1, wherein the resistance change layer includes a metal oxide layer.

11. A semiconductor device according to claim 10, wherein the resistance change layer includes an oxide of copper.

12. A semiconductor device according to claim 1, wherein the first wiring and the second wiring are formed of metal containing 95 wt % or more copper.

13. A semiconductor device according to claim 1, wherein the second wiring has a dual damascene structure.

14. A semiconductor device according to claim 1, wherein the second wiring layer is a wiring layer which is immediately above the first wiring layer.

15. A method of manufacturing a semiconductor device comprising:

forming a first wiring layer on a substrate, the first wiring layer having first wiring formed therein;

forming a first via interlayer insulating film on the first wiring layer;

forming a via hole for a switch element in the first via interlayer insulating film, the via hole for a switch element being located on the first wiring;

forming a resistance change layer at least at a bottom of the via hole for a switch element; and

forming a second wiring layer on the first via interlayer insulating film, the second wiring layer having second wiring formed therein, the second wiring being connected to the resistance change layer.

16. A method of manufacturing a semiconductor device according to claim 15, wherein the forming a resistance change layer includes oxidizing at least a surface of the first wiring exposed at the bottom of the via hole for a switch element.

17. A method of manufacturing a semiconductor device according to claim 15, further comprising, between the forming a via hole for a switch element and the forming a resistance change layer, forming a lower electrode layer in the via hole for a switch element,

wherein the forming a resistance change layer includes oxidizing at least a surface of the lower electrode layer.

18. A method of manufacturing a semiconductor device according to claim 17, wherein the forming a resistance change layer includes oxidizing the entire lower electrode layer.

19. A method of manufacturing a semiconductor device according to claim 15, further comprising, after the forming a resistance change layer and before the forming a second wiring layer, embedding a conductor in the via hole for a switch element,

wherein the forming a second wiring layer comprises:

forming an inter-wiring-layer insulating film on the conductor and on the first via interlayer insulating film;

forming a wiring groove in the inter-wiring-layer insulating film, the conductor being exposed at a bottom of the wiring groove, and forming in the first via interlayer insulating film a via hole for a wiring via, the via hole for a wiring via connecting the wiring groove and the first wiring; and

forming the second wiring and a wiring via for connecting the first wiring and the second wiring by embedding metal in the wiring groove and the via hole for a wiring via.