TRANSISTOR, SEMICONDUCTOR DEVICE INCLUDING THE TRANSISTOR, AND MANUFACTURING METHOD OF THE TRANSISTOR AND THE SEMICONDUCTOR DEVICE

• US 20100207118A1
• Filed: 02/04/2010
• Published: 08/19/2010
• Est. Priority Date: 02/13/2009
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: GODO, Hiromichi, SAKATA, Junichiro, SHIMAZU, Takashi
• Granted Patent: US 8,278,657 B2
• Time in Patent Office: Days
• US Class Current: 257/43
• CPC Class Codes: H01L 29/78669 with inverted-type structure, e.g. with bottom gate
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

To suppress deterioration in electrical characteristics in a transistor including an oxide semiconductor layer or a semiconductor device including the transistor. In a transistor in which a channel layer is formed using an oxide semiconductor, a silicon layer is provided in contact with a surface of the oxide semiconductor layer. Further, the silicon layer is provided in contact with at least a region of the oxide semiconductor layer, in which a channel is formed, and a source electrode layer and a drain electrode layer are provided in contact with regions of the oxide semiconductor layer, over which the silicon layer is not provided.

Claims

1. A transistor comprising:

a gate electrode;

a gate insulating layer provided over the gate electrode;

an oxide semiconductor layer provided over the gate insulating layer and overlapping with the gate electrode;

a silicon layer provided over and in contact with a surface of the oxide semiconductor layer; and

a source electrode layer and a drain electrode layer electrically connected to the oxide semiconductor layer.

2. The transistor according to claim 1,

wherein the silicon layer is provided over and in contact with a part of the surface of the oxide semiconductor layer, and

wherein the source electrode layer and the drain electrode layer are provided over and in contact with at least a part of the surface of the oxide semiconductor layer, over which the silicon layer is not provided.

3. The transistor according to claim 2,

wherein a first low-resistance region serving as a source region is provided in a region of the oxide semiconductor layer, which is in contact with the source electrode layer, and

wherein a second low-resistance region serving as a drain region is provided in a region of the oxide semiconductor layer, which is in contact with the drain electrode layer.

4. The transistor according to claim 1,

wherein the oxide semiconductor layer includes at least one of indium, zinc, and gallium.

5. A semiconductor device comprising the transistor according to claim 1.

6. A transistor comprising:

a gate electrode;

a gate insulating layer provided over the gate electrode;

an oxide semiconductor layer provided over the gate insulating layer and overlapping with the gate electrode;

a silicon layer provided over and in contact with a part of a surface of the oxide semiconductor layer;

a first metal oxide layer and a second metal oxide layer provided over and in contact with at least a part of the surface of the oxide semiconductor layer, over which the silicon layer is not provided;

a source electrode layer electrically connected to the first metal oxide layer; and

a drain electrode layer electrically connected to the second metal oxide layer.

7. The transistor according to claim 6,

wherein the oxide semiconductor layer includes at least one of indium, zinc, and gallium.

8. A semiconductor device comprising the transistor according to claim 6.

9. A transistor comprising:

a gate electrode;

a gate insulating layer provided over the gate electrode;

a source electrode layer and a drain electrode layer provided over the gate insulating layer;

an oxide semiconductor layer provided over the source electrode layer and the drain electrode layer and provided over the gate electrode with the gate insulating layer interposed therebetween; and

a silicon layer provided over and in contact with a surface of the oxide semiconductor layer.

10. The transistor according to claim 9,

wherein the oxide semiconductor layer includes at least one of indium, zinc, and gallium.

11. A semiconductor device comprising the transistor according to claim 9.

12. A manufacturing method of a transistor, comprising the steps of:

forming a gate electrode over a substrate;

forming a gate insulating layer over the gate electrode;

forming an oxide semiconductor layer over the gate insulating layer so as to overlap with the gate electrode;

forming a silicon layer so as to cover the oxide semiconductor layer;

etching the silicon layer to expose a part of the oxide semiconductor layer;

forming a conductive film over the silicon layer and the oxide semiconductor layer; and

etching the conductive film to form a source electrode layer and a drain electrode layer.

13. The manufacturing method of a transistor according to claim 12,

wherein the source electrode layer and the drain electrode layer are formed in contact with at least parts of the exposed oxide semiconductor layer.

14. The manufacturing method of a transistor according to claim 12,

wherein the silicon layer is formed by a DC sputtering method.

15. A manufacturing method of a transistor, comprising the steps of:

forming a gate electrode over a substrate;

forming a gate insulating layer over the gate electrode;

forming an oxide semiconductor layer over the gate insulating layer so as to overlap with the gate electrode;

forming a silicon layer so as to cover the oxide semiconductor layer;

etching the silicon layer to expose a part of the oxide semiconductor layer;

performing plasma treatment on the exposed oxide semiconductor layer to form a low-resistance region;

forming a conductive film over the silicon layer and the oxide semiconductor layer; and

etching the conductive film to form a source electrode layer and a drain electrode layer.

16. The manufacturing method of a transistor according to claim 15,

wherein the source electrode layer and the drain electrode layer are formed in contact with at least parts of the exposed oxide semiconductor layer.

17. The manufacturing method of a transistor according to claim 15,

wherein the silicon layer is formed by a DC sputtering method.