SEMICONDUCTOR DEVICE INCLUDING A TRANSISTOR, AND MANUFACTURING METHOD OF THE SEMICONDUCTOR DEVICE

• US 20100207119A1
• Filed: 02/04/2010
• Published: 08/19/2010
• Est. Priority Date: 02/13/2009
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: GODO, Hiromichi, SAKATA, Junichiro, SHIMAZU, Takashi
• Granted Patent: US 8,350,261 B2
• Time in Patent Office: Days
• US Class Current: 257/43
• CPC Class Codes: H01L 21/02554 Oxides
• CPC Class Codes: H01L 21/02565 Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
• CPC Class Codes: H01L 21/02631 Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

The object is to suppress deterioration in electrical characteristics in a semiconductor device comprising a transistor including an oxide semiconductor layer. In a transistor in which a channel layer is formed using an oxide semiconductor, a p-type silicon layer is provided in contact with a surface of the oxide semiconductor layer. Further, the p-type silicon layer is provided in contact with at least a region of the oxide semiconductor layer, in which a channel is formed, and a source electrode layer and a drain electrode layer are provided in contact with regions of the oxide semiconductor layer, over which the p-type silicon layer is not provided.

Claims

1. A semiconductor device comprising:

a gate electrode;

a gate insulating layer provided over the gate electrode;

an oxide semiconductor layer provided over the gate insulating layer and overlapped with the gate electrode;

a silicon layer provided over and in contact with a surface of the oxide semiconductor layer; and

a source electrode layer and a drain electrode layer electrically connected to the oxide semiconductor layer,

wherein the silicon layer has a p-type conductivity.

2. The semiconductor device according to claim 1,

wherein the source electrode layer, and the drain electrode layer are provided over and in contact with a part of the surface of the oxide semiconductor layer, and

wherein the part of the surface of the oxide semiconductor layer is at least a part of region where the silicon layer and the oxide semiconductor layer are not in contact with each other.

3. The semiconductor device according to claim 2,

wherein a first low-resistance region functioning as a source region is provided in a first region of the oxide semiconductor layer,

wherein the first region is in contact with the source electrode layer,

wherein a second low-resistance region functioning as a drain region is provided in a second region of the oxide semiconductor layer, and

wherein the second region is in contact with the drain electrode layer.

4. The semiconductor device according to claim 1, wherein the whole region of the oxide semiconductor layer is located over the gate electrode.

5. The semiconductor device according to claim 1, wherein the oxide semiconductor layer includes at least one of indium, zinc, and gallium.

6. A semiconductor device comprising:

a gate electrode;

a gate insulating layer provided over the gate electrode;

an oxide semiconductor layer provided over the gate insulating layer and overlapped with the gate electrode;

a silicon layer provided over and in contact with part of a surface of the oxide semiconductor layer;

a first metal oxide layer and a second metal oxide layer provided over and in contact with part of the surface of the oxide semiconductor layer, wherein the part of the surface of the oxide semiconductor layer is at least a part of region where the silicon layer and the oxide semiconductor layer are not in contact with each other,

a source electrode layer which is electrically connected to the first metal oxide layer; and

a drain electrode layer which is electrically connected to the second metal oxide layer,

wherein the silicon layer has a p-type conductivity.

7. The semiconductor device according to claim 6,

wherein the first metal oxide layer and the second metal oxide layer includes the same material, and

wherein resistance of the first metal oxide layer and the second metal oxide layer is lower than that of the oxide semiconductor layer.

8. The semiconductor device according to claim 6,

wherein the first metal oxide layer and the second metal oxide layer includes the same material, and

wherein the first metal oxide layer and the second metal oxide layer are provided using the same material as that of the oxide semiconductor layer and under different deposition conditions.

9. The semiconductor device according to claim 6, wherein the whole region of the oxide semiconductor layer is located over the gate electrode.

10. The semiconductor device according to claim 6, wherein the oxide semiconductor layer includes at least one of indium, zinc, and gallium.

11. A semiconductor device comprising:

a gate electrode;

a gate insulating layer provided over the gate electrode;

a source electrode layer and a drain electrode layer provided over the gate insulating layer;

an oxide semiconductor layer provided over the gate insulating layer, the source electrode layer, and the drain electrode layer and overlapped with the gate electrode; and

a silicon layer provided over and in contact with a surface of the oxide semiconductor layer,

wherein the source electrode layer and the drain electrode layer are electrically connected to the oxide semiconductor layer, and

wherein the silicon layer has a p-type conductivity.

12. The semiconductor device according to claim 11, wherein the whole region of the oxide semiconductor layer is located over the gate electrode.

13. The semiconductor device according to claim 11, wherein the oxide semiconductor layer includes at least one of indium, zinc, and gallium.

14. A manufacturing method of a semiconductor device, comprising the steps of:

forming a gate electrode over a substrate;

forming a gate insulating layer over the gate electrode;

forming an oxide semiconductor layer over the gate insulating layer to overlap with the gate electrode;

forming a silicon layer to cover the oxide semiconductor layer;

etching the silicon layer to expose part of the oxide semiconductor layer;

forming a conductive film over the silicon layer and the oxide semiconductor layer; and

etching the conductive film to form a source electrode layer and a drain electrode layer,

wherein the silicon layer has a p-type conductivity.

15. The manufacturing method of a semiconductor device according to claim 14, wherein the source electrode layer and the drain electrode layer are formed to be in contact with at least a part of the exposed part of the oxide semiconductor layer.

16. The manufacturing method of a semiconductor device according to claim 14, wherein the silicon layer is formed by a DC sputtering method.

17. A manufacturing method of a semiconductor device, comprising the steps of:

forming a gate electrode over a substrate;

forming a gate insulating layer over the gate electrode;

forming an oxide semiconductor layer over the gate insulating layer to overlap with the gate electrode;

forming a silicon layer to cover the oxide semiconductor layer;

etching the silicon layer to expose part of the oxide semiconductor layer;

performing plasma treatment on the exposed part of the oxide semiconductor layer to form low-resistance regions, wherein resistance of the low-resistance regions lower than that of the oxide semiconductor layer;

forming a conductive film over the silicon layer and the oxide semiconductor layer; and

etching the conductive film to form a source electrode layer and a drain electrode layer,

wherein the silicon layer has a p-type conductivity.

18. The manufacturing method of a semiconductor device according to claim 17, wherein the source electrode layer and the drain electrode layer are formed to be in contact with at least a part of the low-resistance regions.

19. The manufacturing method of a semiconductor device according to claim 17, wherein the silicon layer is formed by a DC sputtering method.