METHOD FOR PRODUCING A COPPER CONTACT

• US 20100207177A1
• Filed: 12/18/2009
• Published: 08/19/2010
• Est. Priority Date: 06/29/2007
• Status: Abandoned Application

• Current Assignee: IMEC International, Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: IMEC International, Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Zhao, Chao, Tokei, Zsolt, Demuynck, Steven, Beyer, Gerald, Palmans, Roger, Liu, Chung-Shi, Yu, Chen-Hua
• Application Number:
  US12/641,945
• Publication Number:
  US 20100207177A1
• Time in Patent Office: Days
• US Class Current: 257/288
• CPC Class Codes: H01L 21/76831 in via holes or trenches, e.g. non-conductive sidewall liners
• CPC Class Codes: H01L 21/76843 formed in openings in a dielectric
• CPC Class Codes: H01L 21/76855 After-treatment introducing at least one additional element into the layer
• CPC Class Codes: H01L 21/76856 by treatment in plasmas or gaseous environments, e.g. nitriding a refractory metal liner
• CPC Class Codes: H01L 21/76864 Thermal treatment
• CPC Class Codes: H01L 21/76873 for electroplating
• CPC Class Codes: H01L 23/485 consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts H01L23/4821, H01L23/4822, H01L23/4824, H01L23/4825 take precedence; materials H01L23/532, bond pads H01L24/02, bump connectors H01L24/10
• CPC Class Codes: H01L 23/53238 Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A method for producing a contact through the pre-metal dielectric (PMD) layer of an integrated circuit, between the front end of line and the back end of line, and the device produced thereby are disclosed. The PMD layer includes oxygen. In one aspect, the method includes producing a hole in the PMD, depositing a conductive barrier layer at the bottom of the hole, depositing a CuMn alloy on the bottom and side walls of the hole, filling the remaining portion of the hole with Cu. The method further includes performing an anneal process to form a barrier on the side walls of the hole, wherein the barrier has an oxide including Mn. The method further includes performing a CMP process.

Claims

1. A method of producing a contact through a pre-metal dielectric (PMD) layer of an integrated circuit between front end of line and back end of line areas, wherein the PMD layer comprises oxygen, the method comprising:

producing a hole in the PMD layer;

depositing a conductive barrier layer at the bottom of the hole;

depositing a CuMn alloy on the bottom and side walls of the hole;

filling the remaining portion of the hole with Cu;

performing an anneal process to form a barrier on the side walls of the hole, the barrier comprising an oxide comprising Mn; and

performing a CMP process.

2. The method according to claim 1, wherein the conductive barrier layer is a CoWP layer or a CoWB layer.

3. The method according to claim 2, wherein the conductive barrier layer further comprises N in grain boundaries of the CoWP or CoWB.

4. The method according to claim 1, wherein the barrier layer is produced by electroless metal deposition.

5. The method according to claim 1, further comprising a plasma treatment process after the process of depositing the conductive barrier layer, to enhance the barrier properties of the layer.

6. The method according to claim 5, wherein the plasma treatment process takes place with a plasma being generated from a gaseous mixture comprising at least nitrogen and/or NH₃.

7. The method according to claim 1, wherein the PMD comprises Si and wherein the barrier comprises a layer of MnSi_xO_y with x between 0 and 100% and y higher than 0%.

8. The method according to claim 1, wherein the conductive barrier layer comprises copper.

9. The method according to claim 1, wherein the conductive barrier layer has a thickness between 10 nm and 100 nm.

10. The method according to claim 1, wherein the PMD layer is located between interconnect levels and one or more of the following:

a gate, a source, or a drain area.

11. The method according to claim 1, wherein the gate, a source, or a drain area comprises silicide.

12. The method according to claim 1, wherein the CMP process removes excess Cu.

13. A semiconductor device manufactured by a process comprising the method according to claim 1.

14. A method of manufacturing process of a semiconductor device, the method comprising the method according to claim 1.

15. A semiconductor device comprising:

Cu contact vias through a pre-metal dielectric (PMD) layer, the layer comprising oxygen, the contact vias located between source/drain/gate areas and a metal interconnect region, wherein a conductive barrier layer is present at the bottom of the vias and wherein a barrier comprising an oxide comprising Mn is present at the sidewalls of the vias.

16. The device according to claim 15, wherein the conductive barrier layer comprises CoWP or CoWB.

17. The device according to claim 16, wherein the conductive barrier layer further comprises N in grain boundaries of the CoWP or CoWB.

18. The device according to claim 15, wherein the PMD layer comprises Si and wherein the barrier layer on the side walls comprises MnSi_xO_y with x between 0 and 100% and y higher than 0%.

19. The device according to claim 15, wherein the conductive barrier layer has a thickness between 10 nm and 100 nm.

20. The device according to claim 15, wherein the source, drain, or gate area comprises silicide.