NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME

• US 20100207186A1
• Filed: 02/16/2010
• Published: 08/19/2010
• Est. Priority Date: 02/17/2009
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Uenaka, Tsuneo, HIGASHI, Kazuyuki
• Granted Patent: US 8,680,604 B2
• Time in Patent Office: Days
• US Class Current: 257/314
• CPC Class Codes: H10B 43/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/50 characterised by the boundary region between the core and peripheral circuit regions

Abstract

A first region comprises: a semiconductor layer including a columnar portion, a charge storage layer, and a plurality of first conductive layers. The second region comprises: a plurality of second conductive layers formed in the same layer as the plurality of first conductive layers. The plurality of first conductive layers configure a stepped portion at an end vicinity of the first region. The stepped portion is formed in a stepped shape such that positions of ends of the plurality of first conductive layers differ from one another. The plurality of second conductive layers is formed such that positions of ends thereof at an end vicinity of the second region surrounding the first region are aligned in substantially the perpendicular direction to the substrate.

Claims

1. A nonvolatile semiconductor memory device, comprising:

a first region configured to function as a plurality of memory strings, each of which has a plurality of electrically rewritable memory cells connected in series; and

a second region provided in a periphery of the first region,

the first region comprising;

a first semiconductor layer including a columnar portion extending in a perpendicular direction with respect to a substrate;

a charge storage layer formed on a side surface of the columnar portion; and

a plurality of first conductive layers formed on the charge storage layer, and configured to function as a control electrode of the memory cells,

and

the second region comprising a plurality of second conductive layers formed in the same layer as the plurality of first conductive layers,

the plurality of first conductive layers configuring a stepped portion at an end vicinity of the first region, the stepped portion being formed in a stepped shape such that positions of ends of the plurality of first conductive layers differ from one another, and

the plurality of second conductive layers being formed such that positions of ends thereof at an end vicinity of the second region surrounding the first region are aligned in substantially the perpendicular direction to the substrate.

2. The nonvolatile semiconductor memory device according to claim 1,

wherein the stepped portion includes a plurality of steps arranged in a line in a first direction parallel to the substrate.

3. The nonvolatile semiconductor memory device according to claim 1,

further comprising a select transistor connected to one end of the memory strings,

the select transistor comprising:

a second semiconductor layer extending from the columnar portion in the perpendicular direction;

a gate insulating layer formed on a side surface of the second semiconductor layer; and

a third conductive layer formed on the gate insulating layer and configured to function as a control electrode of the select transistor,

the third conductive layer being formed in stripes parallel to the substrate, the stripes having a certain pitch in a second direction and extending in a third direction orthogonal to the second direction.

4. The nonvolatile semiconductor memory device according to claim 3,

wherein the stepped portion includes a plurality of steps arranged in a line in the second direction.

5. The nonvolatile semiconductor memory device according to claim 3,

wherein the stepped portion includes a plurality of steps arranged in a line in the third direction.

6. The nonvolatile semiconductor memory device according to claim 1,

wherein the stepped portion includes a plurality of steps arranged in a matrix in a fourth direction and a fifth direction parallel to the substrate.

7. The nonvolatile semiconductor memory device according to claim 2,

wherein the stepped portion comprises:

a first stepped portion formed so as to decrease in height in a stepwise manner proceeding from a first position to a second position in the first direction, and to increase in height in a stepwise manner proceeding from the second position to a third position in the first direction; and

a second stepped portion formed so as to decrease in height in a stepwise manner proceeding from the third position to a fourth position in the first direction, and to increase in height in a stepwise manner proceeding from the fourth position to a fifth position in the first direction,

the first stepped portion and the second stepped portion each having an asymmetrical shape.

8. A nonvolatile semiconductor memory device, comprising:

a first region configured to function as a plurality of memory strings, each of which has a plurality of electrically rewritable memory cells connected in series,

the first region comprising;

a semiconductor layer including a columnar portion extending in a perpendicular direction with respect to a substrate;

a charge storage layer formed on a side surface of the columnar portion;

a plurality of conductive layers formed on the charge storage layer, and configured to function as a control electrode of the memory cells;

a stepped portion having the plurality of conductive layers formed in a stepped shape such that positions of ends of the plurality of conductive layers differ from one another; and

a wall portion provided adjacently to the stepped portion and formed by the plurality of conductive layers such that positions of ends of the plurality of conductive layers are aligned in substantially the perpendicular direction to the substrate.

9. The nonvolatile semiconductor memory device according to claim 8,

wherein the stepped portion includes a plurality of steps arranged in a line in a first direction parallel to the substrate.

10. The nonvolatile semiconductor memory device according to claim 8,

wherein the first region further functions as a select transistor connected to one end of the memory strings,

and wherein the first region further comprises:

a second semiconductor layer extending from the columnar portion in the perpendicular direction;

a gate insulating layer formed on a side surface of the second semiconductor layer; and

a third conductive layer formed on the gate insulating layer and configured to function as a control electrode of the select transistor,

the third conductive layer being formed in stripes parallel to the substrate, the stripes having a certain pitch in a second direction and extending in a third direction orthogonal to the second direction.

11. The nonvolatile semiconductor memory device according to claim 10,

wherein the stepped portion includes a plurality of steps arranged in a line in the second direction.

12. The nonvolatile semiconductor memory device according to claim 10,

wherein the stepped portion includes a plurality of steps arranged in a line in the third direction.

13. The nonvolatile semiconductor memory device according to claim 8,

wherein the stepped portion includes a plurality of steps arranged in a matrix in a fourth direction and a fifth direction parallel to the substrate.

14. The nonvolatile semiconductor memory device according to claim 9,

wherein the stepped portion comprises:

a first stepped portion formed so as to decrease in height in a stepwise manner proceeding from a first position to a second position in the first direction, and to increase in height in a stepwise manner proceeding from the second position to a third position in the first direction; and

a second stepped portion formed so as to decrease in height in a stepwise manner proceeding from the third position to a fourth position in the first direction, and to increase in height in a stepwise manner proceeding from the fourth position to a fifth position in the first direction,

the first stepped portion and the second stepped portion each having an asymmetrical shape.

15. A method of manufacturing a nonvolatile semiconductor memory device, the nonvolatile semiconductor memory device including a first region configured to function as a plurality of memory strings, each of which has a plurality of electrically rewritable memory cells connected in series, and a second region provided in a periphery of the first region, comprising:

depositing a plurality of conductive layers on a substrate;

dividing the plurality of conductive layers to form a plurality of first conductive layers positioned in the first region and a plurality of second conductive layers positioned in the second region;

penetrating the plurality of first conductive layers to form a penetration hole;

forming a charge storage layer in a side surface of the penetration hole;

forming a first semiconductor layer so as to fill the penetration hole; and

forming the plurality of first and second conductive layers such that, at an end vicinity of the first region, the plurality of first conductive layers configure a stepped portion formed in a stepped shape such that positions of ends of the plurality of first conductive layers differ from one another, and such that, at an end vicinity of the second region surrounding the first region, the plurality of second conductive layers have positions of ends thereof aligned in substantially the perpendicular direction to the substrate.

16. The method of manufacturing a nonvolatile semiconductor memory device according to claim 15,

wherein the stepped portion includes a plurality of steps arranged in a line in a first direction parallel to the substrate.

17. The method of manufacturing a nonvolatile semiconductor memory device according to claim 15,

wherein the stepped portion includes a plurality of steps arranged in a matrix in a second direction and a third direction parallel to the substrate.

18. The method of manufacturing a nonvolatile semiconductor memory device according to claim 17, further comprising:

forming a first resist layer on the first conductive layer;

repeatedly executing a slimming of the first resist layer in the second direction and an etching of the first conductive layer;

forming a second resist layer on the first conductive layer; and

repeatedly executing a slimming of the second resist layer in the third direction and an etching of the first conductive layer.

19. The method of manufacturing a nonvolatile semiconductor memory device according to claim 16,

wherein the stepped portion comprises:

a first stepped portion formed so as to decrease in height in a stepwise manner proceeding from a first position to a second position in the first direction, and to increase in height in a stepwise manner proceeding from the second position to a third position in the first direction; and

a second stepped portion formed so as to decrease in height in a stepwise manner proceeding from the third position to a fourth position in the first direction, and to increase in height in a stepwise manner proceeding from the fourth position to a fifth position in the first direction,

the first stepped portion and the second stepped portion each having an asymmetrical shape.

20. The method of manufacturing a nonvolatile semiconductor memory device according to claim 19, further comprising:

forming a first resist layer on the first conductive layer;

repeatedly executing a slimming of the first resist layer in the first direction and an etching of the first conductive layer;

forming a second resist layer on the first conductive layer, the second resist layer including a trench; and

repeatedly executing a slimming of the second resist layer from the trench in the third direction and an etching of the first conductive layer.