Structures and Methods for Improving Trench-Shielded Semiconductor Devices and Schottky Barrier Rectifier Devices

• US 20100207205A1
• Filed: 02/19/2009
• Published: 08/19/2010
• Est. Priority Date: 02/19/2009
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Dolny, Gary, Probst, Dean E., Grebs, Thomas E., Rinehimer, Mark, Yedinak, Joseph, Benjamin, John
• Granted Patent: US 8,148,749 B2
• Time in Patent Office: Days
• US Class Current: 257/334
• CPC Class Codes: H01L 2223/54426 for alignment
• CPC Class Codes: H01L 2223/54453 for use prior to dicing
• CPC Class Codes: H01L 23/544 Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 29/0657 characterised by the shape of the body
• CPC Class Codes: H01L 29/66143 Schottky diodes
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/872 Schottky diodes
• CPC Class Codes: H01L 29/8725 of the trench MOS barrier type [TMBS]
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

Various structures and methods for improving the performance of trench-shielded power semiconductor devices and the like are described.

Claims

1. A semiconductor device comprising:

a semiconductor region having a surface;

a first area of the semiconductor region;

a well region of a first conductivity type disposed in the semiconductor region and around the first area; and

a plurality of trenches extending in a semiconductor region, each trench having a first end disposed in a first portion of the well region, a second end disposed in a second portion of the well region, and a middle portion between the first and second ends and disposed in the first area, each trench further having opposing sidewalls lined with a dielectric layer, and a conductive electrode disposed on at least a portion of the dielectric layer.

2. The semiconductor device of claim 1, wherein at least a portion of the well region has a surface that is recessed below the surface of the semiconductor region, and wherein the bottoms of the first and second end portions of each trench lies below the bottom of the middle portion of the trench.

3. The semiconductor device of claim 1, wherein the trenches are disposed parallel to one another.

4. The semiconductor device of claim 3, further comprising a first end trench disposed in the well region, the first end trench having a first end, a second end, opposing sidewalls lined with a dielectric layer, and a conductive electrode disposed on at least a portion of the dielectric layer, the first end trench being further disposed to one side of the plurality of trenches and parallel to the plurality of trenches.

5. The semiconductor device of claim 4, wherein the first end trench has a width that is in the range of 0.8 times to 1.2 times the width of a trench of the plurality of trenches.

6. The semiconductor device of claim 4, further comprising a first mesa disposed between two adjacent trenches of the plurality of trenches, and a second mesa disposed between the first end trench and the plurality of trenches, wherein the second mesa has a width that is in the range of 0.8 times to 1.2 times the width of a trench of the first mesa.

7. The semiconductor device of claim 4, further comprising a second end trench disposed in the well region, the second end trench having a first end, a second end, opposing sidewalls lined with a dielectric layer, and a conductive electrode disposed on at least a portion of the dielectric layer, the second end trench being further disposed perpendicular to the first ends of the plurality of trenches.

8. The semiconductor device of claim 7, wherein the first ends of the first and second end trenches are joined together.

9. The semiconductor device of claim 8, wherein at least a portion of the well region has a surface that is recessed below the surface of the semiconductor region, and wherein the bottoms of the first and second end portions of each trench lies below the bottom of the middle portion of the trench, and wherein the bottoms of the first and second end trenches lie below the bottom of the middle portion of at least one of the other trenches.

10. The semiconductor device of claim 3, further comprising an end trench disposed in the well region, the end trench having a first end, a second end, opposing sidewalls lined with a dielectric layer, and a conductive electrode disposed on at least a portion of the dielectric layer, the end trench being further disposed perpendicular to the first ends of the plurality of trenches.

11. The semiconductor device of claim 1, further comprising a perimeter trench disposed in the well region and encircling the plurality of trenches.

12. The semiconductor device of claim 1, further comprising an active region of a second conductivity type opposite to the first conductivity type disposed in the semiconductor region and within the first area thereof.

13. The semiconductor device of claim 1, wherein the well region has a surface that is flush with the surface of the semiconductor region

14. A photomask for defining a plurality of trenches at a first surface of a semiconductor wafer, the semiconductor wafer having a first area at its first surface, a second area at its first surface and adjacent to the first area, and a peripheral edge between the first and second areas, the first area being at a different height relative to the second area, the photomask comprising:

an alignment mark for aligning the photomask to the peripheral edge between the first and second areas of the semiconductor wafer;

an array of striped regions for defining a plurality of trenches in the first surface of the semiconductor wafer, each striped region having a first portion to be aligned within the first area of the semiconductor wafer and a second portion to be aligned within the second area, wherein the first portion of the striped region has a first width and the second portion of the striped region has a second width, wherein the first width is different from the second width.

15. The photomask of claim 14, wherein the first width is wider than the second width.

16. The photomask of claim 14, wherein the second width is wider than the first width.

17. The photomask of claim 14, wherein each striped region further has a third portion disposed between its first and second portions, the third portion to be aligned in the second area of the semiconductor wafer but with an edge abutting the peripheral edge, wherein the third portion has a width that is closer to the first width than the second width, and a length of a first value.

18. The photomask of claim 17, wherein the width of the third portion is substantially equal to the first width.

19. The photomask of claim 17, wherein the length of the third portion is not more than 10 microns.

20. The photomask of claim 17, wherein the length of the third portion is in a range spanning from 0.2 microns to 5 microns.

21. The photomask of claim 17, wherein the length of the third portion is in a range spanning from 0.5 microns to 2 microns.

22. The photomask of claim 17, wherein the peripheral edge has a portion running substantially parallel to the array of striped regions, wherein the striped region of said array that is closest to said portion of the peripheral edge is to be aligned so that it is spaced from said portion by at least the first value.

23. The photomask of claim 17, wherein the peripheral edge has a portion running substantially parallel to the array of striped regions, wherein the photomask further comprises a first striped region disposed on one side of the array of striped regions, wherein the first striped region is to be aligned so that it is spaced from said portion of the peripheral edge by a distance equal to or less than the first value, and wherein the first striped region has a width that is closer to the first width than the second width.

24. The photomask of claim 23, wherein the width of the first striped region is equal to the first width.

25. The photomask of claim 23, wherein the photomask further comprises a second striped region disposed adjacent to the first striped region, wherein the second striped region is to be aligned within the second portion of the first area of the semiconductor wafer, and wherein the second striped region has a width that is closer to the first width than the second width.

26. The photomask of claim 25, wherein the width of the second striped region is equal to the first width.

27. The photomask of claim 14, further comprising an end striped region disposed adjacent to first portions of the plurality of striped regions, wherein the end striped region is to be aligned within the first area of the semiconductor wafer, and wherein the end striped region has a width that is closer to the first width than the second width.

28. The photomask of claim 27, wherein the width of the end striped region is equal to the first width.

29. The photomask of claim 14, wherein the height of the first area is below the height of the second area.

30. The photomask of claim 14, wherein the height of the first area is above the height of the second area.

31. The photomask of claim 14, wherein at least one of the first and second widths is less than one micron.

32. A photomask set comprising:

a photomask according to claim 14; and

a second photomask for defining the first area in the first surface of the semiconductor wafer.

33. A method of manufacturing a semiconductor device with one or more trenches, the method comprising:

forming one or more initial trenches into a semiconductor region, each trench having a bottom wall and one or more side walls;

growing a sacrificial oxide layer on the walls of the initial trenches;

removing the sacrificial oxide layer;

forming a dielectric layer on the side and bottom walls of the one or more trenches after removing the sacrificial oxide layer; and

filling the one or more trenches with electrically conductive material.

34. The method of claim 33, wherein forming the initial trenches comprises plasma etching the semiconductor region with a fluorine-based gas through a patterned etch mask.

35. The method of claim 34, wherein the patterned etch mask comprises a patterned photoresist layer.

36. The method of claim 34, wherein the patterned etch mask comprises a patterned oxide layer.

37. The method of claim 33, wherein forming the initial trenches comprises plasma etching the semiconductor region with a chlorine-based gas through a patterned etch mask.

38. The method of claim 37, wherein the patterned etch mask comprises a patterned photoresist layer.

39. The method of claim 37, wherein the patterned etch mask comprises a patterned oxide layer.

40. The method of claim 34, wherein the plasma etching of the semiconductor region with the fluorine-based gas is a first plasma etching, and wherein forming the initial trenches further comprises exposing the initial trenches to a second plasma etching that has a lower energy impact on the semiconductor material.

41. The method of claim 33, wherein forming the initial trenches comprises:

plasma etching the semiconductor region with a first etchant gas through a patterned etch mask, the etching properties of the first etchant gas being more anisotropic than isotropic, wherein the first etching gas comprises one or more chemical components; and

thereafter plasma etching the semiconductor region with a second etchant gas, the etching properties of the second etchant gas being more isotropic than the etching properties of the first etchant gas, wherein the second etching gas comprises one or more chemical components.

42. The method of claim 33 wherein growing the sacrificial oxide comprises growing an oxide layer at a temperature of about 1100°

C. or higher.

43. The method of claim 42, wherein the oxide layer grown at a temperature of about 1100°

C. or higher has a thickness of 1000 Angstroms or less.

44. The method of claim 33 further comprising, after removing the sacrificial oxide, growing a second sacrificial oxide layer and removing the second sacrificial oxide layer.

45. The method of claim 33, wherein forming a thin dielectric layer comprises growing an oxide layer on the trench bottom and side walls at a temperature of 1100°

C. or higher in a dry oxygen environment that is diluted with one or more inert gases.

46. The method of claim 45, wherein the oxide layer is grown at a temperature in the range of about 1125°

C. to about 1200°

C., and wherein oxygen comprises 10% to 75% by volume of the gaseous growth environment.

47. The method of claim 45, wherein the oxide layer is grown at a temperature in the range of about 1125°

C. to about 1200°

C., and wherein oxygen comprises 25% to 60% by volume of the gaseous growth environment.

48. A method of manufacturing a semiconductor device with one or more trenches, the method comprising:

forming one or more trenches into a semiconductor region, each trench having a bottom wall and one or more side walls;

growing an oxide layer on the trench bottom and side walls of the one or more trenches at a temperature of 1100°

C. or higher in a dry oxygen environment that is diluted with one or more inert gases; and

filling the one or more trenches with electrically conductive material.

49. The method of claim 48, wherein the oxide layer is grown at a temperature in the range of about 1125°

C. to about 1200°

C., and wherein oxygen comprises 10% to 75% by volume of the gaseous growth environment.

50. The method of claim 48, wherein the oxide layer is grown at a temperature in the range of about 1125°

C. to about 1200°

C., and wherein oxygen comprises 25% to 60% by volume of the gaseous growth environment

51. A semiconductor device comprising:

a semiconductor region having a surface; and

a plurality of trenches extending in a semiconductor region, each trench having a first end, a second end, and a middle portion between the first and second ends, each trench further having opposing sidewalls lined with a dielectric layer, and a conductive electrode disposed on at least a portion of the dielectric layer, wherein the conductive electrode comprises p-doped polysilicon.

52. The semiconductor device of claim 51, wherein at least a portion of the p-doped polysilicon has a net doping level of 1×

10¹⁸ dopant atoms per cubic centimeter (cm<sup>−

3</sup>) or higher.

53. A method of manufacturing a semiconductor device with one or more trenches, the method comprising:

forming one or more trenches into a semiconductor region, each trench having a bottom wall and one or more side walls, the one or more trenches defining surfaces of the semiconductor region that are adjacent to the one or more trenches;

forming a dielectric layer on the side and bottom walls of the one or more trenches; and

filling the one or more trenches with p-doped polysilicon material.

54. The method of claim 53, wherein forming the dielectric layer forms the layer on the surfaces of the semiconductor region that are adjacent to the one or more trenches;

and wherein filling the one or more trenches with p-doped polysilicon material comprises;

depositing a layer of p-doped polysilicon material over the dielectric layer;

annealing the deposited polysilicon material; and

removing a top portion of the annealed polysilicon material.

55. The method of claim 54 wherein at least a portion of the p-doped polysilicon material has a net doping level of 1×

10¹⁸ dopant atoms per cubic centimeter (cm<sup>−

3</sup>) or higher.

56. The method of claim 54, wherein the polysilicon material is deposited at a first temperature, and wherein annealing the deposited polysilicon material comprises heating the deposited polysilicon layer to a second temperature that is greater than the first temperature.

57. The method of claim 53, wherein filling the one or more trenches with p-doped polysilicon material comprises:

depositing a layer of polysilicon material over the dielectric layer and semiconductor region;

implanting a p-type dopant into the polysilicon material;

annealing the implanted polysilicon material; and

removing a top portion of the annealed polysilicon material.

58. The method of claim 57, wherein implanting a p-type dopant comprises implanting the dopant at two or more implant energy levels.

59. The method of claim 57 wherein the implanted dose of the p-type dopant is at least 5×

10¹⁴ dopant atoms per square centimeter.

60. The method of claim 57 wherein the implanted dose of the p-type dopant is in the range of 5×

10¹⁴ dopant atoms per square centimeter to 5×

10¹⁶ dopant atoms per square centimeter.

61. The method of claim 53, wherein forming the dielectric layer forms the layer on the surfaces of the semiconductor region that are adjacent to the one or more trenches;

and wherein filling the one or more trenches with p-doped polysilicon material comprises;

depositing a layer of polysilicon material over the dielectric layer;

annealing the polysilicon material while exposing the polysilicon material to a vapor-phase p-type dopant; and

removing a top portion of the annealed polysilicon material.