TRANSISTOR

• US 20100207206A1
• Filed: 02/11/2010
• Published: 08/19/2010
• Est. Priority Date: 05/19/2004
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Racki, Mathias, Lanzerstorfer, Sven, Ostermann, Thomas, Krischke, Norbert, Zundel, Markus, Vannucci, Nicola
• Granted Patent: US 8,120,135 B2
• Time in Patent Office: Days
• US Class Current: 257/337
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 29/0642 Isolation within the component, i.e. internal isolation
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/7803 structurally associated with at least one other device assemblies H01L25/00; integrated circuits H01L27/00
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7821 the other device being a breakdown diode, e.g. Zener diode

Abstract

A transistor has a cell array with two or more transistor cells, a temperature sensor, which is integrated in the cell array or is adjacent to the cell array, and an isolation structure. The isolation structure isolates the temperature sensor from the cell array, and has an isolation trench, which is arranged between the cell array and the temperature sensor. The distance between the temperature sensor and the active transistor cell that is closest to the temperature sensor corresponds approximately to the pitch between active transistor cells within the cell array.

Claims

1. A transistor device comprising:

a cell array formed in a silicon substrate having a surface with at least two active transistor cells, wherein trenches of the transistor cells are separated by a pitch;

a temperature sensor proximate to the cell array and having an isolation structure configured to electrically isolate the temperature sensor from the cell array, the isolation structure having an isolation trench;

wherein a distance between the temperature sensor and at least one of the active transistor cells that is closest to the temperature sensor corresponds approximately to the pitch between the trenches of the active transistor cells within the cell array; and

wherein the temperature sensor is formed in a portion of or below the surface of the silicon substrate.

2. The transistor of claim 1, wherein the transistor is a trench transistor.

3. The transistor of claim 2, wherein internal walls of a cell array trench that is closest to the isolation trench, as well as internal walls of the isolation trench, are clad with isolation layers.

4. The transistor of claim 2, wherein at least two successive isolation layers in the horizontal direction are thickened over the entire vertical extent of the trench.

5. The transistor of claim 4, wherein the two successive thickened isolation layers are both formed within the isolation trench.

6. The transistor of claim 4, wherein one thickened isolation layer is in each case formed within the isolation trench and the closest cell array trench.

7. The transistor of claim 1, wherein a mesa region configured between the isolation trench and the closest cell array trench is alternatively activated and deactivated.

8. The transistor of claim 1, wherein the transistor cells are DMOS transistor cells.

9. The transistor of claim 1, wherein the temperature sensor is one selected from the group comprising a transistor, a diode, and a resistor.

10. The transistor of claim 3, wherein at least one electrode is provided in the isolation trench.

11. The transistor of claim 10, wherein the potential at the at least one electrode varies in the vertical and horizontal direction.

12. The transistor of claim 11, wherein possible potential values for the at least one electrode are one of the source potential, the gate potential, the drain potential/2, and the substrate potential/2.

13. The transistor of claim 1, wherein the temperature sensor is enclosed by two isolation trenches, wherein the distance between the two isolation trenches is less than the pitch between active transistor cells within the cell array.

14. A transistor device comprising:

a cell array formed in a silicon substrate having a surface and with at least two active transistor cells, wherein trenches of the transistor cells are separated by a pitch; and

a temperature sensor proximate to the cell array and comprising an isolation structure with two isolation trenches;

wherein the isolation structure is configured to electrically isolate the temperature sensor from the cell array;

wherein a distance between the temperature sensor and at least one of the active transistor cells that is closest to the temperature sensor corresponds approximately to the pitch between active transistor cells within the cell array;

wherein a distance between the two isolation trenches of the isolation structure is greater than the pitch between the trenches of the active transistor cells within the cell array; and

wherein the temperature sensor is formed in a portion of or below the surface of the silicon substrate.

15. A transistor component comprising:

a semiconductor body in which at least two transistors that are arranged alongside one another are formed, wherein each transistor includes at least two trenches; and

isolation structures configured to electrically isolate the transistors from one another;

wherein the isolation structures each have an isolation trench; and

wherein a distance between at least one of the isolation trenches and one of the transistors corresponds approximately to a pitch between the trenches of the transistor.

16. The transistor component of claim 15, wherein the isolation trenches represent edge terminations of doped well regions that are formed in edge areas of the transistors.

17. The transistor component of claim 16, wherein the isolation trenches are provided at a distance from the well regions between doped well regions which are in each case formed in edge areas of the transistors.

18. The transistor component of claims 15, wherein the transistors are n-channel MOS transistors.

19. The transistor component of claims 15, wherein the transistors are p-channel MOS transistors.

20. The transistor component of claims 15, wherein an electrode is provided in the isolation trench.

21. The transistor component of claim 20, wherein the potential of the electrode is the substrate potential.

22. The transistor component of claims 15, wherein the transistor component is a trench transistor.

23. The transistor component of claim 22, wherein the isolation trench is produced together with the cell array trench, in one process step.

24. A transistor device comprising:

a cell array formed in a silicon substrate having a surface and having a plurality of transistor cell array trenches separated by a pitch;

a temperature sensor integrated in the cell array and separated from at least one of the plurality of transistor cells by a distance that is approximately the same as the pitch between the trenches of the plurality of transistor cells; and

means for electrically isolating the temperature sensor from the cell array,

wherein the temperature sensor is formed in a portion of or below the surface of the silicon substrate.

25. The transistor of claim 24, further including an isolation trench between the cell array and the temperature sensor.