NANOWIRE MESH DEVICE AND METHOD OF FABRICATING SAME

• US 20100207208A1
• Filed: 02/17/2009
• Published: 08/19/2010
• Est. Priority Date: 02/17/2009
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Sleight, Jeffery W., Bedell, Stephen W., Chang, Josephine B., Guillorn, Michael A., Chang, Paul
• Granted Patent: US 7,893,492 B2
• Time in Patent Office: Days
• US Class Current: 257/346
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: B82Y 40/00 Manufacture or treatment of nanostructures
• CPC Class Codes: H01L 29/0665 the shape of the body defining a nanostructure nanotechnology per se B82B
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/66439 with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor with an active layer made of a group 13/15 material H01L29/66469
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66772 Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates H01L29/66666 takes precedence; thin film FinFETs H01L29/66795
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/775 with one dimensional charge carrier gas channel, e.g. quantum wire FET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621
• CPC Class Codes: Y10S 977/72 On an electrically conducting, semi-conducting, or semi-insulating substrate
• CPC Class Codes: Y10S 977/742 Carbon nanotubes, CNTs
• CPC Class Codes: Y10S 977/762 Nanowire or quantum wire, i.e. axially elongated structure having two dimensions of 100 nm or less
• CPC Class Codes: Y10S 977/938 Field effect transistors, FETS, with nanowire- or nanotube-channel region

Abstract

A semiconductor structure is provided that includes a plurality of vertically stacked and vertically spaced apart semiconductor nanowires (e.g., a semiconductor nanowire mesh) located on a surface of a substrate. One end segment of each vertically stacked and vertically spaced apart semiconductor nanowires is connected to a source region and another end segment of each vertically stacked and vertically spaced apart semiconductor nanowires is connected to a drain region. A gate region including a gate dielectric and a gate conductor abuts the plurality of vertically stacked and vertically spaced apart semiconductor nanowires, and the source regions and the drain regions are self-aligned with the gate region.

Claims

1. A semiconductor structure comprising:

a plurality of vertically stacked and vertically spaced apart semiconductor nanowires located on a surface of a substrate, each semiconductor nanowire having two end segments in which one of the end segments is connected to a source region and the other end segment is connected to a drain region; and

a gate region including a gate dielectric and a gate conductor over at least a portion of the plurality of vertically stacked and vertically spaced apart semiconductor nanowires, wherein each source region and each drain region is self-aligned with the gate region.

2. The semiconductor structure of claim 1 wherein each of said semiconductor nanowires has a pitch of less than 200 nm and a width of less than 40 nm.

3. The semiconductor structure of claim 1 wherein each of said semiconductor nanowires comprises a Si-containing semiconductor material.

4. The semiconductor structure of claim 1 wherein each of said semiconductor nanowires has a height variation of less than or equal to 5%.

5. The semiconductor structure of claim 1 further comprising a spacer located between each vertically stacked and vertically spaced apart semiconductor nanowire and between the gate region and the source region and drains region.

6. The semiconductor structure of claim 1 wherein each vertically spaced apart semiconductor nanowire is separated by a distance of less than 200 nm.

7. The semiconductor structure of claim 1 further comprising an interfacial oxide layer located on each semiconductor nanowire, said interfacial oxide having a thickness of less than 5 nm.

8. The semiconductor structure of claim 1 wherein a sacrificial material layer is located atop the source region and drain region and surrounding the gate region, said sacrificial material layer having an upper surface that is coplanar with an upper surface of the gate region.

9. A semiconductor structure comprising:

a plurality of vertically stacked and vertically spaced apart silicon nanowires located on a surface of a buried insulating layer of an semiconductor-on-insulator substrate, each silicon nanowire having two end segments in which one of the end segments is connected to a source region and the other end segment is connected to a drain region and each of said silicon nanowires has a pitch of less than 200 nm, a width of less than 40 nm and a height variation of less than or equal to 5%;

a gate region including a gate dielectric and a gate conductor over at least a portion of the plurality of vertically stacked and vertically spaced apart silicon nanowires, wherein each source region and each drain region is self-aligned with the gate region; and

a sacrificial material layer located atop the source region and drains region and surrounding the gate region, said sacrificial material layer having an upper surface that is coplanar with an upper surface of the gate region.

10. The semiconductor structure of claim 9 wherein each vertically spaced apart silicon nanowire is separated by a distance of less than 200 nm.

11. The semiconductor structure of claim 9 further comprising an interfacial oxide layer located on each silicon nanowire, said interfacial oxide having a thickness of less than 5 nm.

12. The semiconductor structure of claim 9 further comprising a spacer located between each vertically stacked and spaced apart silicon nanowire and between the gate region and each source region and each drain region.

13. A method of forming a semiconductor structure comprising:

providing a plurality of patterned hard masks atop a patterned material stack including alternating layers of semiconductor material and sacrificial material, wherein the bottommost layer of the patterned material stack is a top semiconductor layer of a semiconductor substrate;

forming at least one dummy gate over a central portion of each of said plurality of patterned hard masks;

forming a sacrificial material layer abutting said at least one dummy gate;

removing the at least one dummy gate to form at least one trench in the sacrificial material layer, each trench centered over the central portion of the plurality of patterned hard masks, that distinguishes a fin region from source and drain regions;

etching a plurality of fins within said at least one trench in the patterned material stack using the plurality of patterned hard masks as an etch mask;

removing the plurality of patterned hard masks and each layer of sacrificial material within said at least one trench to form a plurality of vertically stacked and vertically spaced apart semiconductor nanowires within said at least one trench; and

filling the at least one trench with at least a gate region.

14. The method of claim 13 wherein said semiconductor substrate is a semiconductor-on-insulator and said bottommost layer of said patterned material stack is located on a buried insulating layer.

15. The method of claim 13 wherein said alternating layers of sacrificial material and semiconductor material excluding said top semiconductor layer are formed by an epitaxial growth process, said epitaxial growth process is performed at a temperature of below 800°

C. and at a pressure below 100 torr.

16. The method of claim 15 wherein each of said layers of sacrificial materials are semiconductor materials that are doped in-situ during said epitaxial growth process.

17. The method of claim 13 further comprising forming a spacer within said at least one trench between said removing the plurality of patterned hard masks and removing each layer of sacrificial material within said at least one trench, said spacer is formed by deposition and etching, and said etching is performed utilizing a large over etch such that no spacer material remains on the sidewalls of each fin.

18. The method of claim 13 wherein said removing each layer of sacrificial material is performed chemically utilizing an etchant that exploits the lower oxidation potential of the layers of sacrificial material compared to the layers of semiconductor material.

19. The method of claim 13 wherein said removing each layer of sacrificial material is performed utilizing a plasma etching process.

20. The method of claim 13 wherein said removing each layer of sacrificial material is performed using a wet or dry oxidation process that is performed at a temperature of less than 750°

C.

21. The method of claim 13 further comprising performing a solid source diffusion anneal between said removing the plurality of patterned hard masks and each layer of sacrificial material within said at least one trench and filling the at least one trench with at least a gate region, said solid source diffusion anneal forms source regions and drain regions in said layers of semiconductor material outside said at least one trench.

22. The method of claim 21 wherein said solid source diffusion anneal is performed in an inert ambient at a temperature of 800°

C. or greater.

23. The method of claim 13 further comprising performing a differential chemical oxidation process between said removing the plurality of patterned hard masks and each layer of sacrificial material within said at least one trench and filling the at least one trench with at least a gate region to form at least an interfacial oxide on said semiconductor nanowires.

24. The method of claim 23 wherein said differential chemical oxidation process is performed in an oxygen-containing ambient.

25. The method of claim 13 wherein each semiconductor nanowire has a pitch of less than 200 nm and a width of less than 40 nm.