CHIP PACKAGE AND MANUFACTURING METHOD THEREOF

• US 20100207258A1
• Filed: 02/19/2009
• Published: 08/19/2010
• Est. Priority Date: 02/19/2009
• Status: Active Grant

• Current Assignee: Advanced Semiconductor Engineering Inc (ASE Technology Holding Co., Ltd.)
• Original Assignee: Advanced Semiconductor Engineering Inc (ASE Technology Holding Co., Ltd.)
• Inventors: Kim, Dukman, Eun, Younghyo
• Granted Patent: US 8,110,902 B2
• Time in Patent Office: Days
• US Class Current: 257/660
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 23/055 the leads having a passage through the base H01L23/057 takes precedence
• CPC Class Codes: H01L 23/3121 a substrate forming part of the encapsulation
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/552 Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00011 Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/19041 being a capacitor
• CPC Class Codes: H01L 2924/207 Diameter ranges
• CPC Class Codes: H01L 2924/30107 Inductance
• CPC Class Codes: H01L 2924/3025 Electromagnetic shielding

Abstract

A chip package including at least a shielding layer for better electromagnetic interferences shielding is provided. The shielding layer disposed over the top surface of the laminate substrate can protect the chip package from the underneath EMI radiation. The chip package may further include another shielding layer over the molding compound of the chip package.

Claims

1. A chip package, comprising:

a laminate substrate having a plurality of contacts thereon;

at least a chip disposed on the laminate substrate;

a first shielding layer disposed over the laminate substrate, exposing the contacts and the chip;

a molding compound, at least encapsulating the chip, the contacts, a portion of the first shielding layer and a portion of the laminate substrate; and

a second shielding layer, disposed over the molding compound and covering the molding compound.

2. The chip package as claimed in claim 1, wherein first shielding layer further has a plurality of first openings exposing the contact, and the sizes of the first openings are large than those of the correspondingly exposed contacts.

3. The chip package as claimed in claim 1, wherein the chip is disposed on a die pad of the laminate substrate and is electrically connected to the contacts through a plurality of wires.

4. The chip package as claimed in claim 1, wherein the chip is electrically connected to the contacts through a plurality of bumps arranged underneath the chip.

5. The chip package as claimed in claim 3, wherein first shielding layer further has at least a second opening exposing the chip, and the size of the second opening is not smaller than that of the die pad.

6. The chip package as claimed in claim 4, wherein first shielding layer further has at least a second opening exposing the chip, and the size of the second opening is larger than that of an area of the arranged bumps.

7. The chip package as claimed in claim 1, wherein the chip is a radio frequency chip.

8. The chip package as claimed in claim 1, wherein the second shielding layer is electrically connected to at least a ground via of the laminate substrate.

9. The chip package as claimed in claim 1, a material of the first shielding layer is a solder material.

10. The chip package as claimed in claim 1, a material of the second shielding layer is a solder material.

11. A manufacturing method of a chip package, comprising:

providing a substrate having a plurality of contacts and a die attaching region thereon;

forming a first shielding layer over a top surface of the substrate, wherein the contacts and the die attaching region are exposed by the first shielding layer;

disposing at least a chip on the die attaching region of the substrate, wherein the chip is electrically connected to the substrate;

forming a molding compound on the substrate to encapsulate the chip, the contacts and at least a portion of the first shielding layer; and

forming a second shielding layer over the molding compound.

12. The method as claimed in claim 11, wherein the first shielding layer is formed by a screen printing process.

13. The method as claimed in claim 11, wherein the second shielding layer is formed by a screen printing process or a plating process.

14. The method as claimed in claim 11, wherein the second shielding layer is formed to cover an exposed surface of the molding compound and at least a ground via of the substrate.

15. The method as claimed in claim 11, wherein the die attaching region includes a die pad, and the chip is electrically connected to the substrate through wire bonding.

16. The method as claimed in claim 11, wherein the chip is electrically connected to the substrate through flip chip bonding.