Advanced Pixel Design for Optimized Driving

• US 20100207861A1
• Filed: 02/13/2009
• Published: 08/19/2010
• Est. Priority Date: 02/13/2009
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Apple Inc.
• Inventors: Zhong, John Z., Chang, Shih Chang
• Granted Patent: US 8,390,553 B2
• Time in Patent Office: Days
• US Class Current: 345/90
• CPC Class Codes: G09G 2300/0426 Layout of electrodes and connections
• CPC Class Codes: G09G 2300/0443 with several sub-pixels for the same colour in a pixel, not specifically used to display gradations G09G3/364 takes precedence
• CPC Class Codes: G09G 2320/0209 Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display
• CPC Class Codes: G09G 3/3614 Control of polarity reversal in general
• CPC Class Codes: G09G 3/3655 Details of drivers for counter electrodes, e.g. common electrodes for pixel capacitors or supplementary storage capacitors

Abstract

Systems, devices, and methods for reducing common voltage loading and/or enabling a simplified manner of polarity inversion in liquid crystal display (LCD) devices are provided. In accordance with one embodiment, a device may include a processor, a memory device, and a liquid crystal display having a pixel array including rows and columns of pixels. The pixels of each row of the pixel array may be configured to cause an approximately even amount of common voltage loading to be shared between one of a first plurality of common electrodes and one of a second plurality of common electrodes when the pixels of each row of the pixel array receive a scanning signal and a data signal.

Claims

1. A fringe-field switching display panel comprising:

a pixel array including rows and columns of pixels, each pixel including;

a pixel electrode;

a portion of one of a plurality of common electrodes disposed beneath the pixel electrode and shared by a plurality of pixels of the pixel array; and

a transistor having a gate coupled to one of a plurality of gate lines of the pixel array and coupled to the portion of the one of the plurality of common electrodes;

wherein the pixel array is configured such that, upon activation of a gate line of the plurality of gate lines, common voltage loading resulting from the activation is shared by at least two of the plurality of common electrodes.

2. The display panel of claim 1, wherein the pixel array includes a row of pixels having a first plurality of pixels connected to a first gate line of the plurality of gate lines and a second plurality of pixels connected to a second gate line of the plurality of gate lines.

3. The display panel of claim 2, wherein odd-numbered pixels of the row of pixels are connected to the first gate line and even-numbered pixels are connected to the second gate line.

4. The display panel of claim 1, wherein the pixel array includes first and second adjacent rows of pixels, and wherein at least one common electrode of the plurality of common electrodes is shared by only some of the pixels of the first row and by only some of the pixels of the second row.

5. The display panel of claim 4, wherein the at least one common electrode includes conductive elements of alternating pixels of the first and second rows that are electrically coupled to one another via conductive lines.

6. A device comprising:

a processor;

a memory device operably coupled to the processor and configured to store video data; and

a liquid crystal display configured to display the video data by one video frame at a time, the liquid crystal display having a pixel array including rows and columns of pixels, each pixel including;

a pixel electrode;

a portion of either one of a first plurality of common electrodes or one of a second plurality of common electrodes configured to generate an electric field in conjunction with the pixel electrode; and

a transistor having a gate connected to one of a plurality of gate lines of the pixel array and a source connected to one of a plurality of source lines of the pixel array, wherein the transistor is configured to provide a data signal from the source line to the pixel electrode when a scanning signal is received on the gate line;

wherein the pixels of each row of the pixel array are configured to cause an approximately even amount of common voltage loading to be shared between one of the first plurality of common electrodes and one of the second plurality of common electrodes when the pixels of each row of the pixel array receive a scanning signal and a data signal.

7. The device of claim 6, wherein all even-numbered pixels of each row of the pixel array include a portion of a single one of the first plurality of common electrodes and wherein all odd-numbered pixels of each row of the pixel array include a portion of a single one of the second plurality of common electrodes.

8. The device of claim 6, wherein, for even-numbered video frames, the first plurality of common electrodes is configured to receive a first common voltage and the second plurality of common electrodes is configured to receive a second common voltage and wherein, for odd-numbered video frames, the first plurality of common electrodes is configured to receive the second common voltage and the second plurality of common electrodes is configured to receive the first common voltage.

9. The device of claim 8, wherein the first common voltage and the second common voltage are of opposite polarities.

10. The device of claim 6, wherein each pixel of the pixel array is configured such that no directly horizontally or directly vertically adjacent pixel includes a portion of a common electrode carrying the same polarity of common voltage.

11. A display panel comprising:

a pixel array including rows and columns of pixels, each pixel including;

a pixel electrode;

a portion of one of a plurality of common electrodes shared by a plurality of pixels of the pixel array and configured to generate an electric field in conjunction with the pixel electrode; and

a transistor having a gate coupled to one of a plurality of gate lines of the pixel array and a source coupled to one of a plurality of source lines of the pixel array, wherein the transistor is configured to activate the pixel electrode when a scanning signal is received on the gate line and a data signal is received on the source line;

wherein a first row of pixels of the pixel array shares a first common electrode of the plurality of common electrodes with a second row of pixels of the pixel array and shares a second common electrode of the plurality of common electrodes with a third row of pixels of the pixel array.

12. The display panel of claim 11, wherein the first row of pixels is directly adjacent to the second row of pixels or the third row of pixels.

13. The display panel of claim 12, wherein the first row of pixels is directly adjacent to both the second row of pixels and the third row of pixels.

14. The display panel of claim 11, wherein even-numbered pixels of the first row of pixels share the first common electrode with the second row of pixels and wherein odd-numbered pixels of the first row of pixels share the second common electrode with the third row of pixels.

15. The display panel of claim 14, wherein the first common electrode is shared with odd-numbered pixels of the second row and wherein the second common electrode is shared with even-numbered pixels of the third row.

16. The display panel of claim 15, wherein the first common electrode is connected between one of the even-numbered pixels of the first row of pixels and one of the odd-numbered pixels of the second row of pixels by at least one line of Indium Tin Oxide.

17. The display panel of claim 11, wherein all pixels of the first row of pixels are connected to a single gate line of the plurality of gate lines, wherein the single gate line is shared only by the pixels of the first row of pixels.

18. The display panel of claim 17, wherein the first row of pixels is configured such that, upon activation of the single gate line, common voltage loading resulting from activation is shared approximately evenly by the first common electrode and the second common electrode.

19. The display panel of claim 11, wherein the first common electrode is configured to carry a first common voltage and the second common electrode is configured to carry a second common voltage.

20. The display panel of claim 19, wherein the first common voltage and the second common voltage are of opposite polarities.

21. The display panel of claim 19, wherein the pixels of the first row of pixels are connected to the first common electrode and the second common electrode such that the pixels of the first row of pixels receive alternating polarities of common voltage.

22. A method of controlling a liquid crystal display comprising:

supplying a first common voltage to a first plurality of common electrodes of a pixel array, wherein the pixel array comprises rows and columns of pixels, wherein each row of pixels is connected to a respective gate line and each column of pixels is connected to a respective source line, and wherein a first plurality of pixels of each row is connected to one of the first plurality of common electrodes;

supplying a second common voltage to a second plurality of common electrodes of the pixel array, wherein a second plurality of pixels of each row is connected to one of the second plurality of common electrodes;

supplying a scanning signal to a gate line corresponding respectively to one of the rows of pixels; and

supplying a data signal to each source line corresponding respectively to each pixel of the one of the rows of pixels.

23. The method of claim 22, wherein supplying the first common voltage to the first plurality of common electrodes comprises supplying the first common voltage to approximately half of the common electrodes of the pixel array and wherein supplying the second common voltage to the second plurality of common electrodes comprises supplying the second common voltage to approximately half of the common electrodes of the pixel array.

24. The method of claim 22, wherein the first common voltage is supplied to the first plurality of common electrodes, wherein the first plurality of pixels of each row is connected to one of the first plurality of common electrodes and wherein the first plurality of pixels of each row comprises every even-numbered pixel.

25. The method of claim 24, wherein the second common voltage is supplied to the second plurality of common electrodes, wherein the second plurality of pixels of each row is connected to one of the second plurality of common electrodes and wherein the second plurality of pixels of each row comprises every odd-numbered pixel.

26. The method of claim 25, wherein the first common voltage supplied to the first plurality of common electrodes and the second common voltage supplied to the second plurality of common electrodes are of opposite polarities.

27. The method of claim 22, wherein supplying the first common voltage to the first plurality of common electrodes comprises supplying the first common voltage to even-numbered common electrodes of the pixel array, and wherein supplying the second common voltage to the second plurality of common electrodes comprises supplying the second common voltage to odd-numbered common electrodes of the pixel array.

28. A method of controlling a liquid crystal display comprising:

supplying a first common voltage to a first plurality of common electrodes of a pixel array, wherein the pixel array includes rows and columns of pixels and wherein the even-numbered pixels of each row of pixels are connected to one of the first plurality of common electrodes;

supplying a second common voltage to a second plurality of common electrodes of the pixel array, wherein the odd-numbered pixels of each row of pixels are connected to one of the second plurality of common electrodes; and

activating each row of pixels of the pixel array one at a time until all rows have been activated for a first video frame, wherein common voltage loading resulting from each activation is shared approximately evenly between the one of the first plurality of common electrodes and the one of the second plurality of common electrodes.

29. The method of claim 28, wherein the first common voltage supplied and the second common voltage supplied are of opposite polarities.

30. The method of claim 28, comprising, after all rows have been activated for the first video frame, supplying the second common voltage to the first plurality of common electrodes, supplying the first common voltage to the second plurality of common electrodes, and activating each row of pixels of the pixel array one at a time until all rows have been activated for a second video frame.