READ ONLY MEMORY AND METHOD OF READING SAME
First Claim
1. A Read Only Memory (ROM) device operating at a supply voltage, comprising:
- a ROM array including a plurality of bit line columns connected to a plurality of bit lines, each of the plurality of bit line columns comprising a plurality of bit cells, wherein a gate terminal of each of the plurality of bit cells is connected to a plurality of word lines, and wherein the plurality of word lines operate at a level shifted voltage that is higher than the supply voltage;
a row address decoder connected to the ROM array, wherein for a read operation, the row address decoder selects at least one of the plurality of word lines;
a column address decoder connected to the plurality of bit lines, wherein for the read operation, the column address decoder generates a column address signal for enabling at least one of the plurality of bit lines, and wherein the column address signal operates at the level shifted voltage;
one or more sense amplifiers connected to the plurality of bit lines for sensing the plurality of bit lines;
one or more column multiplexers connected to the plurality of bit line columns, wherein the one or more column multiplexers comprise;
a plurality of transmission gates connected to the plurality of bit lines for transferring data stored in the plurality of bit cells to the one or more sense amplifiers, wherein the column address signal is supplied to a gate terminal of an n-channel metal oxide semiconductor field effect transistor (n-MOSFET) of the plurality of transmission gates;
an inverter circuit for receiving the column address signal and generating a pull-down bit line signal to discharge the at least one enabled bit line, wherein the pull-down bit line signal operates at the level shifted voltage; and
a control circuit connected to the row address decoder, the one or more column multiplexers, and the one or more sense amplifiers, wherein the control circuit generates a pull-up bit line signal for pre-charging the plurality of bit lines, wherein the pull-up bit line signal operates at the level shifted voltage, and generates a sense amplifier enable signal for enabling the one or more sense amplifiers, wherein the sense amplifier enable signal operates at the level shifted voltage, and the one or more sense amplifiers perform the read operation.
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Accused Products
Abstract
A Read Only Memory (ROM) device includes a ROM array, a row address decoder, a column address decoder, a column multiplexer, and a control circuit. Data is stored in bit cells in the ROM array. The control circuit generates control signals for reading the ROM. The row address decoder selects a word line. The column address decoder enables a bit line. The data is sensed from a bit cell corresponding to the selected word line and the enabled bit line by a corresponding sense amplifier and delivered on a data output pin of the ROM. The control signals for enabling the bit line and the sense amplifier operate at a higher voltage than supply voltage of the ROM. This reduces the ROM read time.
15 Citations
19 Claims
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1. A Read Only Memory (ROM) device operating at a supply voltage, comprising:
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a ROM array including a plurality of bit line columns connected to a plurality of bit lines, each of the plurality of bit line columns comprising a plurality of bit cells, wherein a gate terminal of each of the plurality of bit cells is connected to a plurality of word lines, and wherein the plurality of word lines operate at a level shifted voltage that is higher than the supply voltage; a row address decoder connected to the ROM array, wherein for a read operation, the row address decoder selects at least one of the plurality of word lines; a column address decoder connected to the plurality of bit lines, wherein for the read operation, the column address decoder generates a column address signal for enabling at least one of the plurality of bit lines, and wherein the column address signal operates at the level shifted voltage; one or more sense amplifiers connected to the plurality of bit lines for sensing the plurality of bit lines; one or more column multiplexers connected to the plurality of bit line columns, wherein the one or more column multiplexers comprise; a plurality of transmission gates connected to the plurality of bit lines for transferring data stored in the plurality of bit cells to the one or more sense amplifiers, wherein the column address signal is supplied to a gate terminal of an n-channel metal oxide semiconductor field effect transistor (n-MOSFET) of the plurality of transmission gates; an inverter circuit for receiving the column address signal and generating a pull-down bit line signal to discharge the at least one enabled bit line, wherein the pull-down bit line signal operates at the level shifted voltage; and a control circuit connected to the row address decoder, the one or more column multiplexers, and the one or more sense amplifiers, wherein the control circuit generates a pull-up bit line signal for pre-charging the plurality of bit lines, wherein the pull-up bit line signal operates at the level shifted voltage, and generates a sense amplifier enable signal for enabling the one or more sense amplifiers, wherein the sense amplifier enable signal operates at the level shifted voltage, and the one or more sense amplifiers perform the read operation. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A Read Only Memory (ROM) device operating at a supply voltage, comprising:
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a ROM array including a plurality of bit line columns connected to a plurality of bit lines, each of the plurality of bit line columns comprising a plurality of bit cells, wherein a gate terminal of each of the plurality of bit cells is connected to a plurality of word lines, and wherein the plurality of word lines operate at a level shifted voltage that is higher than the supply voltage; a row address decoder connected to the ROM array, wherein for a read operation, the row address decoder selects at least one of the plurality of word lines; a column address decoder connected to the plurality of bit lines, wherein for the read operation, the column address decoder generates a column address signal for enabling at least one of the plurality of bit lines, and wherein the column address signal operates at the level shifted voltage; one or more sense amplifiers connected to the plurality of bit lines for sensing the plurality of bit lines; one or more column multiplexers connected to the plurality of bit line columns, wherein the one or more column multiplexers comprise; a plurality of transmission gates connected to the plurality of bit lines for transferring data stored in the plurality of bit cells to the one or more sense amplifiers, wherein the column address signal is supplied to a gate terminal of an n-channel metal oxide semiconductor field effect transistor (NMOSFET) of the plurality of transmission gates; an inverter circuit for receiving the column address signal and generating a pull-down bit line signal to discharge the at least one enabled bit line; and a control circuit connected to the row address decoder, the one or more column multiplexers, and the one or more sense amplifiers, wherein the control circuit generates a pull-up bit line signal for pre-charging the plurality of bit lines, and generates a sense amplifier enable signal for enabling the one or more sense amplifiers, the one or more sense amplifiers performing the read operation. - View Dependent Claims (9, 10, 11, 12, 13, 14, 15)
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16. A method for operating a Read Only Memory (ROM) device, the ROM operating at a supply voltage and including a ROM array, the ROM array including a plurality of bit line columns connected to a plurality of bit lines, each of the plurality of bit line columns comprising a plurality of bit cells, wherein a gate terminal of each of the plurality of bit cells is connected to a plurality of word lines, the method comprising the steps of:
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generating a column address signal for enabling at least one of the plurality of bit lines, wherein the column address signal operates at a level shifted voltage that is higher than the supply voltage; generating a pull-up bit line signal for pre-charging the plurality of bit lines, wherein the pull-up bit line signal operates at the level shifted voltage; disabling the pull-up bit line signal based on the plurality of bit lines being pre-charged to a first predefined threshold voltage; generating a row address signal for selecting at least one of the plurality of word lines for a read operation, wherein the plurality of word lines operate at the level shifted voltage; enabling one or more sense amplifiers associated with each of the plurality of bit lines by a sense amplifier enable signal, wherein the sense amplifier enable signal operates at the level shifted voltage, and the one or more sense amplifiers perform the read operation; generating a pull-down bit line signal by disabling the column address signal, wherein the pull-down bit line signal discharges the enabled one of the plurality of bit lines, and wherein the pull-down bit line signal operates at the level shifted voltage; and disabling the selected one of the plurality of word lines by disabling the row address signal for completing the read operation. - View Dependent Claims (17, 18, 19)
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Specification