Nonvolatile memory device, method of operating nonvolatile memory device and memory system including nonvolatile memory device

• US 20100208521A1
• Filed: 02/16/2010
• Published: 08/19/2010
• Est. Priority Date: 02/17/2009
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Jang, Jun-Ho, Kim, Nam-Hoon
• Granted Patent: US 8,203,881 B2
• Time in Patent Office: Days
• US Class Current: 365/185.90
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits

Abstract

The method of operating the nonvolatile memory device may include performing a read operation on a first address region, comparing a read time of the first address region with a reference time, and storing read data from the read from the first address region in a second address region based on the comparison result.

Claims

1. A method for operating a nonvolatile memory device, comprising:

performing a read operation on a first address region;

comparing a read time of the first address region with a reference time; and

storing read data from the first address region in a second address region based on the comparison result.

2. The operation method of claim 1, wherein the storing stores the read data in the second address region if a result of the comparing indicates that the read time of the first address region is longer than the reference time.

3. The operation method of claim 2, wherein the performing the read operation on the first address region comprises:

sensing data of memory cells corresponding to the first address region; and

correcting errors of the sensed data.

4. The operation method of claim 3, wherein the read time of the first address includes a sensing time of the sensed data and a post-sensing time of the corrected errors.

5. The operation method of claim'"'"' 1, wherein the performing the read operation on the first address region comprises:

sensing data of memory cells corresponding to the first address region; and

correcting errors of the sensed data.

6. The operation method of claim 5, wherein the storing the read data in the second address region includes storing in the second address regions the corrected sensed data.

7. The operation method of claim 6, wherein the correcting includes discriminating whether sensed data represents an erased state or programmed state

8. The operation method of claim 5, wherein the correcting includes discriminating whether sensed data represents an erased state or programmed state

9. The operation method of claim 5, wherein the read time of the first address includes a sensing time of the sensed data and a post-sensing time of the corrected errors.

10. The operation method of claim 1, wherein,

the storing includes counting a number of times that the read time of the first address region is longer than the reference time, and

the storing stores the read data in the second address region if a result of the counting indicates that the counted number is greater than a threshold value.

11. The operation method of claim 10, wherein the performing the read operation on the first address region comprises:

sensing data of memory cells corresponding to the first address region; and

correcting errors of the sensed data.

12. The operation method of claim 11, wherein the read time of the first address includes a sensing time of the sensed data and a post-sensing time of the corrected errors.

13. The operation method of claim 12, wherein, the reference time is an integer multiple of an average of the read time of the first address region.

14. The operation method of claim 1, wherein, the reference time is an integer multiple of an average of the read time of the first address region.

15. The operation method of claim 1, further comprising:

mapping an access to the first address region to the second address region such that the first address region becomes unavailable if the storing stores the read data in the second address region.

16. A nonvolatile memory device comprising:

a memory cell array;

a read/write circuit configured to write data in the memory cell array and readout data from the memory cell array; and

a control logic configured to control the read/write circuit according to the method of claim 1, wherein

the control logic controls the read/write circuit so that the read data is stored in the second address region of the memory cell array if the read time of the first address region of the memory cell array is longer than the reference time.

17. The nonvolatile memory device of claim 16, wherein,

the control logic includes an error correction unit, and

the read time of the first address includes a sensing time where memory cells corresponding to the first address region are sensed and a post-sensing time where errors of the sensed data are corrected by the error correction unit.

18. A memory system comprising:

a nonvolatile memory device; and

a controller configured to control the nonvolatile memory device according to the method of claim 1, wherein

the controller is configured to control the nonvolatile memory device so that the read data is stored in the second address region of the nonvolatile memory device if the read time of the first address region of the nonvolatile memory device is longer than the reference time.

19. The memory system of claim 18, wherein the nonvolatile memory device and the controller form a solid state disk/drive.

20. The memory system of claim 18, wherein the nonvolatile memory device and the controller form a memory card.