MEMORY CIRCUIT ARRANGEMENT AND METHOD FOR THE PRODUCTION THEREOF

• US 20100210076A1
• Filed: 05/03/2010
• Published: 08/19/2010
• Est. Priority Date: 04/29/2003
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Schwetzer, Thomas, Kakoschke, Ronald, Gruber, Wolfgang, Wegertseder, Dominik
• Granted Patent: US 8,004,869 B2
• Time in Patent Office: Days
• US Class Current: 438/129
• CPC Class Codes: G11C 5/025 Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device geometrical lay-out of the components in integrated circuits, H01L27/0207
• CPC Class Codes: H01L 25/18 the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A memory circuit arrangement and fabrication method thereof are presented in which the parts of the memory circuit arrangement are situated on two different substrates. An integrated memory cell array is situated on one substrate. An integrated control circuit that controls access to the memory cells is situated on the other (logic circuit) substrate. The control circuit controls sequences when reading, writing or erasing content of a memory cell. The logic circuit substrate also contains a CPU and encryption coprocessor. The memory circuit contains a sense amplifier, with the aid of which the memory state of a memory cell can be determined, and a decoding circuit that selects a word or bit line.

Claims

1. A method for producing an integrated circuit arrangement, in which the following steps are performed without any restriction by the order specified:

fabricating an integrated memory cell array on a memory cell array substrate using a first sequence of method steps;

fabricating an integrated logic circuit that provide basic functions of the memory cell array on a logic circuit substrate, which is separate from the memory cell substrate, using a second sequence of method steps, which differs from the first sequence;

arranging the integrated memory cell array and the integrated logic circuit to form a memory circuit arrangement, wherein a main area of the integrated memory cell array and a main area of the integrated logic circuit lie in two planes parallel to one another and overlapping one another in a direction normal to the main area;

wherein the logic circuit includes at least one of;

a control circuit contained in the memory circuit, the control circuit controlling sequences when at least one of reading, writing or reading and writing content of a memory cell of the memory cell array, or

a decoding circuit contained in the memory circuit, the decoding circuit selects, in a manner dependent on an address datum, a word line or a bit line connected to a plurality of memory cells of the memory cell array.

2. The method as claimed in claim 1, wherein at least one of:

the first sequence contains at least one of the following method steps which is not contained in the second sequence;

producing deep trenches,

producing at least one of;

a n-type well or n-type layer or a p-type well or p-type layer for voltages of greater than 6 volts,

producing a tunnel oxide,

producing insulated electrodes between two oxide layers,

removing selected electrodes above the insulated electrodes,

producing oxide regions having a thickness of greater than 50 nm, or

producing channel connection zones for voltages of greater than 6 volts, or

the second sequence contains at least one of the following method steps which is not contained in the first sequence;

producing shallow trenches,

producing at least one of;

a n-type well or n-type layer or a p-type well or p-type layer for voltages of less than 5 volts,

producing channel connection zones for voltages of less than 5 volts,

producing at least one metallization layer more than in the first sequence.

3. The method as claimed in claim 2, wherein at least one of:

the deep trenches have a depth of greater than 1 μ

m,

the at least one of the n-type well, n-type layer, p-type well, or p-type layer for voltages of greater than 6 volts has a doping gradient suitable for the voltages of greater than 6 volts at an edge,

the shallow trenches have a depth of less than 1 μ

m,

the at least one of the n-type well, n-type layer, p-type well, or p-type layer for voltages of less than 5 volts is formed for voltages of less than 2.5 volts,

the channel connection zones are formed for voltages of less than 2.5 volts.

4. The method as claimed in claim 1, further comprising arranging the memory cell substrate and the logic circuit substrate using at least one of a rapid chip mounting technique or a 3D integration method.

5. The method as claimed in claim 1, wherein the memory cell is a DRAM memory cell, a SRAM memory cell, a ROM memory cell, an EEPROM memory cell, or a flash memory cell having an ONO layer.