PRODUCTION METHOD FOR SEMICONDUCTOR DEVICE

• US 20100210096A1
• Filed: 02/11/2010
• Published: 08/19/2010
• Est. Priority Date: 01/29/2008
• Status: Active Grant

• Current Assignee: Unisantis Electronics Singapore Pte. Ltd. (NewScope Group Holdings AG)
• Original Assignee: Unisantis Electronics Singapore Pte. Ltd. (NewScope Group Holdings AG)
• Inventors: Masuoka, Fujio, Arai, Shintaro
• Granted Patent: US 8,476,132 B2
• Time in Patent Office: Days
• US Class Current: 438/585
• CPC Class Codes: H01L 21/823885 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823821
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence

Abstract

It is intended to provide a method of producing a semiconductor device, comprising the steps of: providing a substrate on one side of which at least one semiconductor pillar stands; forming a first dielectric film to at least partially cover a surface of the at least one semiconductor pillar; forming a conductive film on the first dielectric film; removing by etching a portion of the conductive film located on a top surface and along an upper portion of a side surface of the semiconductor pillar; forming a protective film on at least a part of the top surface and the upper portion of the side surface of the semiconductor pillar; etching back the protective film to form a protective film-based sidewall on respective top surfaces of the conductive film and the first dielectric film each located along the side surface of the semiconductor pillar; forming a resist pattern for forming a gate line in such a manner that at least a portion of the resist pattern is formed on the top surface of the semiconductor pillar by applying a resist and using lithography; and partially removing by etching the conductive film using the resist pattern as a mask while protecting, by the protective film-based sidewall, the portions of the conductive film and the first dielectric film each located along the side surface of the semiconductor pillar, to form a gate electrode and a gate line extending from the gate electrode.

Claims

1. A method of producing a semiconductor device, comprising the steps of:

providing a substrate on one side of which at least one semiconductor pillar stands;

forming a first dielectric film to at least partially cover a surface of the at least one semiconductor pillar;

forming a conductive film on the first dielectric film;

removing by etching a portion of the conductive film located on a top surface and along an upper portion of a side surface of the semiconductor pillar;

forming a protective film on at least a part of the top surface and the upper portion of the side surface of the semiconductor pillar;

etching back the protective film to form a protective film-based sidewall on respective top surfaces of the conductive film and the first dielectric film each located along the side surface of the semiconductor pillar;

forming a resist pattern for forming a gate line in such a manner that at least a portion of the resist pattern is formed on the top surface of the semiconductor pillar by applying a resist and using lithography; and

partially removing by etching the conductive film using the resist pattern as a mask while protecting, by the protective film-based sidewall, the portions of the conductive film and the first dielectric film each located along the side surface of the semiconductor pillar, to form a gate electrode and a gate line extending from the gate electrode.

2. The method as defined in claim 1, wherein the step of removing by etching a portion of the conductive film located on a top surface and along a upper portion of a side surface of the semiconductor pillar includes the sub-steps of:

forming a second dielectric film on the conductive film to allow the semiconductor pillar to be buried therein;

flattening a top surface of the second dielectric film; and

removing by etching a portion of the conductive film and the second dielectric film each located along the side surface of the semiconductor pillar to form the conductive film and the second dielectric film to have substantially the same height.

10. The method as defined in claim 1, wherein the substrate further has a diffusion region formed in contact with a lower part of the semiconductor pillar.

15. The method as defined in claim 1, further comprising the step of forming, in an upper portion of the semiconductor pillar, a diffusion region having a same conductivity type as that of the diffusion region formed in contact with a lower part of the semiconductor pillar.

3. A method of producing a semiconductor device, comprising the steps of:

providing a substrate on one side of which at least one semiconductor pillar stands, the semiconductor pillar having a stopper film formed on a top surface thereof;

forming a first dielectric film to at least partially cover a surface of the at least one semiconductor pillar;

forming a conductive film on the first dielectric film;

forming a second dielectric film on the conductive film to allow the semiconductor pillar to be buried therein;

flattening a top surface of the resulting product by chemical mechanical polishing (CMP), using the stopper film as a CMP stopper;

removing by etching a portion of the second dielectric film and the conductive film each located along an upper portion of a side surface of the semiconductor pillar to form the conductive film and the second dielectric film to have substantially the same height;

forming a protective film on at least a part of the top surface and the upper portion of the side surface of the semiconductor pillar;

etching back the protective film to form a protective film-based sidewall on respective top surfaces of the conductive film and the first dielectric film each located along the side surface of the semiconductor pillar;

removing the second dielectric film;

forming a resist pattern for forming a gate line in such a manner that at least a portion of the resist pattern is formed on the top surface of the semiconductor pillar by applying a resist and using lithography; and

partially removing by etching the conductive film using the resist pattern as a mask while protecting, by the protective film-based sidewall, the portions of the conductive film and the first dielectric film each located along the side surface of the semiconductor pillar, to form a gate electrode and a gate line extending from the gate electrode.

11. The method as defined in claim 3, wherein the substrate further has a diffusion region formed in contact with a lower part of the semiconductor pillar.

16. The method as defined in claim 3, further comprising the step of forming, in an upper portion of the semiconductor pillar, a diffusion region having a same conductivity type as that of the diffusion region formed in contact with a lower part of the semiconductor pillar.

4. A method of producing a semiconductor device, comprising the steps of:

providing a substrate on one side of which at least one semiconductor pillar stands;

forming a first dielectric film to at least partially cover a surface of the at least one semiconductor pillar;

forming a conductive film on the first dielectric film to allow the semiconductor pillar to be buried therein;

etching an upper portion of the conductive film to remove a portion of the conductive film located on a top surface and along an upper portion of a side surface of the semiconductor pillar;

forming a protective film on at least a part of the top surface and the upper portion of the side surface of the semiconductor pillar;

etching back the protective film to form a protective film-based sidewall on respective top surfaces of the conductive film and the first dielectric film each located along the side surface of the semiconductor pillar;

forming a resist pattern for forming a gate line in such a manner that at least a portion of the resist pattern is formed on the top surface of the semiconductor pillar by applying a resist and using lithography; and

partially removing by etching, using the resist pattern as a mask, the conductive film to form at least a portion of the gate line, and partially removing by etching, using the protective film-based sidewall as a mask, the conductive film and the first dielectric film to form at least a portion of a gate electrode to have the desired film thickness.

5. The method as defined in claim 4, further comprising, as a preprocessing for the etching an upper portion of the conductive film to remove a portion of the conductive film located on a top surface and along an upper portion of a side surface of the semiconductor pillar, the step of flattening a top surface of the conductive film.

7. The method as defined in claim 4, wherein the conductive film is a layered structure film comprising a thin metal film on the side of the first dielectric film, and a polysilicon film.

8. The method as defined in claim 5, wherein the conductive film is a layered structure film comprising a thin metal film on the side of the first dielectric film, and a polysilicon film.

12. The method as defined in claim 4, wherein the substrate further has a diffusion region formed in contact with a lower part of the semiconductor pillar.

17. The method as defined in claim 4, further comprising the step of forming, in an upper portion of the semiconductor pillar, a diffusion region having a same conductivity type as that of the diffusion region formed in contact with a lower part of the semiconductor pillar.

6. A method of producing a semiconductor device, comprising the steps of:

providing a substrate on one side of which at least one semiconductor pillar stands, the semiconductor pillar having a stopper film formed on a top surface thereof;

forming a first dielectric film to at least partially cover a surface of the at least one semiconductor pillar;

forming a conductive film on the first dielectric film to allow the semiconductor pillar to be buried therein;

flattening a top surface of the resulting product by chemical mechanical polishing (CMP), using the stopper film as a CMP stopper;

etching an upper portion of the conductive film to remove a portion of the conductive film located along an upper portion of a side surface of the semiconductor pillar;

forming a protective film on at least a part of the top surface and the upper portion of the side surface of the semiconductor pillar;

etching back the protective film to form a protective film-based sidewall on respective top surfaces of the conductive film and the first dielectric film each located along the side surface of the semiconductor pillar;

forming a resist pattern for forming a gate line in such a manner that at least a portion of the resist pattern is formed on the top surface of the semiconductor pillar by applying a resist and using lithography; and

partially removing by etching, using the resist pattern as a mask, the conductive film to form at least a portion of the gate line, and partially removing by etching, using the protective film-based sidewall as a mask, the conductive film and the first dielectric film to form at least a portion of a gate electrode to have the desired film thickness.

9. The method as defined in claim 6, wherein the conductive film is a layered structure film comprising a thin metal film on the side of the first dielectric film, and a polysilicon film.

13. The method as defined in claim 6, wherein the substrate further has a diffusion region formed in contact with a lower part of the semiconductor pillar.

14. The method as defined in claim 9, wherein the substrate further has a diffusion region formed in contact with a lower part of the semiconductor pillar.

18. The method as defined in claim 6, further comprising the step of forming, in an upper portion of the semiconductor pillar, a diffusion region having a same conductivity type as that of the diffusion region formed in contact with a lower part of the semiconductor pillar.

19. The method as defined in claim 9, further comprising the step of forming, in an upper portion of the semiconductor pillar, a diffusion region having a same conductivity type as that of the diffusion region formed in contact with a lower part of the semiconductor pillar.