GNSS RECEIVER AND SIGNAL TRACKING CIRCUIT AND SYSTEM

• US 20100210206A1
• Filed: 11/14/2008
• Published: 08/19/2010
• Est. Priority Date: 11/15/2007
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Young, Philip John
• Granted Patent: US 8,390,513 B2
• Time in Patent Office: Days
• US Class Current: 455/13.400
• CPC Class Codes: G01S 19/30 code related G01S19/246 takes precedence
• CPC Class Codes: G01S 19/37 Hardware or software details of the signal processing chain

Abstract

A GNSS platform architecture with advanced tracking and search engines. The tracking and search functions are separated into 2 independent engines each highly optimized for their targeted functions.

Claims

1. A GNSS processor comprising a tracking module including, a plurality of correlation blocks for producing a number of correlation values for a number of signals consisting of one or more channels, each correlation block containing a means for removing carrier and multiplying the resulting signal by a code corresponding to an expected feature of the signal such as a Gold code, where each correlation block is enabled to produce one or more taps within a contiguous code phase range, where one or more of the taps may be disabled from the computation to conserve power.

2. The GNSS processor of the previous claim, including a means for adapting the precision or code phase range of the blocks by adjusting the code phase relationship between adjacent taps in the block.

3. The GNSS processor of any of the previous claims including, a means for extending the code phase range covered for a code by chaining 2 or more channels such that the carrier wipeoff and code generation is performed by a master channel, and then passed through additional slave channels, where the code and carrier generation in the slave channels may be disabled to conserve power

4. The GNSS processor of any of the previous claims comprising a means for extending the frequency range the correlator by performing DSP calculations on the correlator outputs, such as a DFT computation, where the DFT lines cover a frequency range centred around the frequency of the code/carrier NCO'"'"'s.

7. The GNSS processor of any of the previous claims comprising a means to select for one or more channels whether the output data structure for the channels contains the complex results from coherent correlation, or the results of the incoherent accumulation.

8. The GNSS processor of any of the previous claims comprising a means for processing a plurality of taps/DFT lines for a channel where the Taps/DFT lines in the output are selectable according to the region of interest to the application, where an additional set of DFT Lines/Taps are implicitly computed to provide a means for noise floor estimation

9. The GNSS processor of any of the previous claims comprising a means for removing a selected feature from the signal being tracked, such as a navigation data message or an additional spreading code, such as used on the pilot channel in Galileo, by modifying the code before application to the correlator. Where the data pattern is applied to the code with a fixed phase relationship such that it remains coherent to the signal data boundaries regardless of the correlation windows phase or length.

10. The GNSS processor of any of the previous claims comprising a means for applying an alternative spreading code to a selected tap of a such a correlator, where the phase relationship of the code applied is fixed or adjustable to ensure that it is in phase with a particular tap of the first spreading code at a particular tap to facilitate the extraction of a data message contained on a second signal which is transmitted using the second spreading code at the same carrier frequency as the first signal whilst the first signal is being used to control the tracking loop.

11. The GNSS processor of any of the previous claims comprising a means for controlling the correlation window size, and/or the number of coherent accumulations applied for each DFT co-efficient in order to control the DFT line spacing of the resulting output

12. The GNSS processor of any of the previous claims comprising a means for selecting the coherent integration alignment by selectively ignoring certain correlator outputs whilst still updating the DFT co-efficient index, such that the coherent accumulation can maintain alignment with a feature of the signal, such as the signal data bit boundaries of the navigation data message, whilst the DFT processing maintains the necessary carrier phase alignment.

14. The GNSS processor of any of the previous claims including adjustment means to adjust the master carrier NCO to compensate for systematic carrier drift due to variations in the reference clock frequency.

15. The GNSS processor of any of the previous claims including means for sampling of all carrier and code NCO values simultaneously across all channels using a trigger such as a pulse from a 1 ms reference timer.

18. The GNSS processor of any of the previous claims wherein the step for the coefficients is determined by the DFT table size, DFT line spacing, and coherent sample index.

19. The GNSS processor of any of the previous claims wherein, by determining a precise start-up time synchronous to a known even, such as a reference timer operated synchronous to the RF reference clock, the precise values for code/carrier phase, code epoch count, navigation data message phase etc can be calculated by extrapolation of measurement from another channel, such as a channel in the search engine, or another tracking channel.

20. The GNSS processor of the previous claim wherein, by programming these values into the configuration of a channel in advance of this time, such that the channel has time to intialize the relevant hardware to the required state, and then programming the exact start time, the channel can pre-initialize engines such as the code generator etc and then freeze them until the instant that it is configured to start.

21. The GNSS processor of any of the previous claims including means of sharing an output memory between multiple correlation engines where the memory is dimensioned according to the overall system requirements rather than the combined data output capability of the complete correlation engine.

22. The GNSS processor of any of the previous claims including means of passing coherent correlation results to the processor for a correlator channel consisting of a set of real time correlation results for a number of TAP/DFT line combinations to facilitate tracking, where in addition to this real time data a historical data set is presented for one or more taps known as the prompt data set, where these taps are selected to be aligned with the spreading code such that they will be at the strongest correlation phase.

5. A GNSS processor comprising a plurality of correlation taps for computing a number of correlations against a plurality of signal codes, such as Gold codes, where the computation windows for each tap are overlapped, where the windows are offset by a deterministic interval, such that the correlation outputs from each tap are separated in time allowing further pipelined processing using a shared resource.

6. The processor of the previous claim, including both coherent and incoherent processing, for example coherent DFT followed by incoherent accumulation of magnitude.

13. A GNSS processor comprising a plurality of correlation taps for computing a number of correlations against a plurality of signal codes, such as Gold codes, including a multi-stage carrier wipeoff mechanism whereby incoming IF/IQ data is mixed with a reference carrier to remove most of the carrier but where the carrier used is configured to leave a residual carrier of for instance 10 Khz. Further removal of the residual carrier is performed by a second carrier NCO in each channel, allowing carrier phase measurements to be used for greater navigation accuracy

16. A GNSS processor comprising a plurality of correlation taps for computing a number of correlations against a plurality of signal codes, such as Gold codes, including a DFT processor wherein DFT calculation is performed by calculating a particular frequency line and then stepping in one direction for a number of lines, then after a number of lines have been computed stepping in the opposite direction offset from a second particular line allowing a subset of the DFT lines to be calculated using simple co-efficient calculation.

17. A GNSS processor of claim 16 where the first particular line calculated is the DFT centre line and the first particular calculated in the second step is the line “

−

1”

.