SYSTEM AND METHOD FOR PROCESSING DIGITAL DATA

• US 20100211712A1
• Filed: 02/17/2010
• Published: 08/19/2010
• Est. Priority Date: 02/18/2009
• Status: Active Grant

• Current Assignee: STMicroelectronics SAS (STMicroelectronics NV)
• Original Assignee: STMicroelectronics SAS (STMicroelectronics NV)
• Inventors: Cauchy, Xavier, Faugeras, Isabelle, Siron, Didier, Philippe, Anthony
• Granted Patent: US 8,527,683 B2
• Time in Patent Office: Days
• US Class Current: 710/110
• CPC Class Codes: G06F 13/4022 using switching circuits, e.g. switching matrix, connection or expansion network G06F13/4009 takes precedence
• CPC Class Codes: G06F 2213/0038 System on Chip
• CPC Class Codes: G06F 9/3877 using a slave processor, e.g. coprocessor peripheral processor G06F13/12; vector processor G06F15/8053
• CPC Class Codes: G06F 9/3885 using a plurality of independent parallel functional units
• CPC Class Codes: G06T 1/20 Processor architectures; Processor configuration, e.g. pipelining

Abstract

This system for processing digital data may include a set of slave processing units for the execution of elementary functions, an interconnection module, which is designed to communicate with a data transfer network and to transfer data between the processing units, on the one hand, and the data transfer network, on the other hand, and a controller controlling the interconnection module to control the data transfer.

Claims

1-13. -13. (canceled)

14. A system-on-chip (SoC) comprising:

a set of slave processing units configured to execute elementary processing functions;

a data transfer SoC network;

an interconnection module configured to communicate with said data transfer SoC network and to transfer data between said set of slave processing units and said data transfer SoC network; and

a controller configured to control the data transfer.

15. The SoC according to claim 14 wherein said set of slave processing units comprises a set of programmable processing units and a set of non-programmable hardware processing units.

16. The SoC according to claim 15 further comprising a shared memory associated with said set of programmable processing units.

17. The SoC according to claim 16 wherein said shared memory comprises a memory internal to said set of programmable processing units.

18. The SoC according to claim 14 wherein said interconnection module disables slave processing units not in demand.

19. The SoC according to claim 18 wherein said interconnection module inserts into a signal transmitted to one of said set of slave processing units an active flag for a transaction in progress, and disables the processing unit if there is no active flag in the transmitted signal.

20. The SoC according to claim 14 wherein said set of slave processing units are organized in groups having stages with non-simultaneous action;

and further comprising a multiplexer for multiplexing the groups of slave processing units.

21. The SoC according to claim 20 wherein said interconnection module inserts into a signal transmitted to each slave processing unit a configuration signal of the respective group.

22. The SoC according to claim 14 further comprising a plurality of parallel sets of slave processing units, each group associated with a local memory and with a local interconnection module.

23. The SoC according to claim 14 wherein said interconnection module transfers video data.

24. A system for processing digital data comprising:

a set of slave processing units configured to execute elementary video processing functions and comprising a set of programmable processing units and a set of non-programmable hardware processing units;

a data transfer network;

an interconnection module configured to communicate with said data transfer network and to transfer video data between said set of slave processing units and said data transfer network; and

a controller configured to control the data transfer.

25. The system according to claim 24 further comprising a shared memory associated with said set of programmable processing units.

26. The system according to claim 24 wherein said interconnection module disables slave processing units not in demand.

27. The system according to claim 26 wherein said interconnection module inserts into a signal transmitted to one of said set of slave processing units an active flag for a transaction in progress, and disables the processing unit if there is no active flag in the transmitted signal.

28. The system according to claim 24 wherein said set of slave processing units are organized in groups having stages, with non-simultaneous action;

and further comprising a multiplexer for multiplexing the groups of slave processing units.

29. A satellite television signal decoder for processing digital data comprising:

a set of slave processing units configured to execute video processing functions;

a data transfer network;

an interconnection module configured to communicate with said data transfer network and to transfer video data between said set of slave processing units and said data transfer network; and

a controller configured to control the data transfer.

30. The satellite television signal decoder according to claim 29 wherein said set of slave processing units comprises a set of programmable processing units and a set of non-programmable hardware processing units.

31. The satellite television signal decoder according to claim 30 further comprising a shared memory associated with said set of programmable processing units.

32. The satellite television signal decoder according to claim 29 wherein said interconnection module disables slave processing units not in demand.

33. The satellite television signal decoder according to claim 29 wherein said interconnection module inserts into a signal transmitted to one of said set of slave processing units an active flag for a transaction in progress, and disables the processing unit if there is no active flag in the transmitted signal.

34. The satellite television signal decoder according to claim 29 wherein said set of slave processing units are organized in groups having stages with non-simultaneous action;

and further comprising a multiplexer for multiplexing the groups of slave processing units.

35. The satellite television signal decoder according to claim 34 wherein said interconnection module inserts into a signal transmitted to each slave processing unit a configuration signal of the respective group.

36. The satellite television signal decoder according to claim 29 wherein said set of slave processing units, said data transfer network, said interconnection module, and said controller are on a System-on-Chip (SoC).

37. A television set processing digital data comprising:

a set of slave processing units configured to execute elementary video processing functions;

a data transfer network;

an interconnection module configured to communicate with said data transfer network and to transfer video data between said set of slave processing units and said data transfer network; and

a controller configured to control the data transfer.

38. The television set according to claim 37 wherein said set of slave processing units comprises a set of programmable processing units and a set of non-programmable hardware processing units.

39. The television set according to claim 38 further comprising a shared memory associated with said set of programmable processing units.

40. The television set according to claim 37 wherein said interconnection module disables slave processing units not in demand.

41. The television set according to claim 37 wherein said interconnection module inserts into a signal transmitted to one of said set of slave processing units an active flag for a transaction in progress, and disables the processing unit if there is no active flag in the transmitted signal.

42. The television set according to claim 37 wherein said set of slave processing units are organized in groups having stages with non-simultaneous action;

and further comprising a multiplexer for multiplexing the groups of slave processing units.

43. The television set according to claim 42 wherein said interconnection module inserts into a signal transmitted to each slave processing unit a configuration signal of the respective group.

44. The television set according to claim 37 wherein said set of slave processing units, said data transfer network, said interconnection module, and said controller are on a System-on-Chip (SoC).

45. A method of making a system for processing digital data on a system-on-chip (SoC), the method comprising:

providing a set of slave processing units for executing elementary processing functions and comprising a set of programmable processing units and a set of non-programmable hardware processing units;

coupling an interconnection module to communicate with a data transfer SoC network and to transfer data between the set of slave processing units and the data transfer SoC network; and

coupling a controller to the interconnection module to control the data transfer.

46. The method according to claim 45 further comprising coupling a shared memory with the set of slave processing units and being associated with the set of programmable processing units.

47. The method according to claim 45 further comprising configuring the interconnection module to disable slave processing units not in demand.

48. The method according to claim 47 further comprising configuring the interconnection module to insert into a signal transmitted to one of the set of slave processing units an active flag for a transaction in progress, and to disable the processing unit if there is no active flag in the transmitted signal.

49. The method according to claim 45 further comprising:

organizing the set of slave processing units in groups having stages with non-simultaneous action; and

coupling a multiplexer for multiplexing the groups of slave processing units.